Techniques for reducing leakage current in memory devices

Details Techniques for reducing leakage current in memory devices Techniques for reducing leakage current in memory devices

2007-07-17

2007-07-17

Lam, David (Department: 2827)

Static information storage and retrieval

Powering

Data preservation

C365S230060, C365S189110

Reexamination Certificate

active

10900246

ABSTRACT:
Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.

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patent: 6370069 (2002-04-01), Brass et al.
patent: 6693012 (2004-02-01), Mouli et al.
Rahul M. Rao, et al.; Circuit Techniques for Gate and Sub-Threshold Leakage Minimization in Future CMOS Technologies; pp. 1-2.

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