Techniques for optimizing electrical performance and layout...

Details Techniques for optimizing electrical performance and layout... Techniques for optimizing electrical performance and layout...

2008-07-29

2008-07-29

Clark, Jasmine J (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S773000, C257S776000, C257SE23011, C257SE23067, C257SE23145, C174S262000, C361S788000, C361S775000, C361S791000, C361S794000, C361S795000

Reexamination Certificate

active

11285912

ABSTRACT:
Techniques are provided for placing and routing vias that conduct signals through a connector between two electrical units. Vias that conduct a first set of signals are placed next to vias that provide return paths for the first set of signals to reduce cross-talk or impedance. Vias that conduct input or output signals can be placed next to vias that provide return paths for the input or output signals to reduce cross-talk. The vias that provide the return paths can conduct, for example, ground signals, power supply signals, or both. Vias that conduct power supply signals can be placed next to vias that provide return paths for the power supply signals to reduce impedance. The vias that provide the return paths for the power supply signals can conduct, for example, ground signals. The via configurations reduce cost and increase yield, and the via configurations are modular.

REFERENCES:
patent: 7239526 (2007-07-01), Bibee
patent: 2006/0267048 (2006-11-01), Chen et al.

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