Techniques for minimizing memory bandwidth used for motion...

Details Techniques for minimizing memory bandwidth used for motion... Techniques for minimizing memory bandwidth used for motion...

2011-01-04

2011-01-04

Rao, Andy S. (Department: 2621)

Pulse or digital communications

Bandwidth reduction or expansion

Television or motion video signal

C375S240120

Reexamination Certificate

active

07864858

ABSTRACT:
In a motion compensation engine, a number of blocks are provided for re-ordering motion vector (MV) reference positions prior to fetch. An MV Sort & Group block outputs MVs one at a time to a Decomposer block. The Decomposer block takes each MV and decomposes it into a series of DRAM read commands consisting of DRAM addresses. This rectangular region is divided into pixel words, which correspond to addressable DRAM words. The addresses are then sent to an Overlap Remover block, which comprises a bitmap corresponding to the DRAM addresses sent to it from the Decomposer block. Before a group is received, the bitmap is cleared by setting all coordinates to “0”. Each address received causes the Overlap Remover to set a bit to “1” in the bitmap which corresponds to a relative (x,y) coordinate within a small bounded rectangular region. Addresses received within a group, which are the same as previous addresses, are overlapping addresses and the corresponding bit will simply remain set to “1”.

REFERENCES:
patent: 5999189 (1999-12-01), Kajiya et al.
patent: 6028612 (2000-02-01), Balakrishnan et al.
patent: 6525783 (2003-02-01), Kim et al.
patent: 7577763 (2009-08-01), Beaman

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