Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1997-10-02
2002-04-16
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S156000, C327S553000, C327S558000
Reexamination Certificate
active
06373304
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to filters and, more particularly, to loop filters for, inter alia, a phase locked loop which maintains a constant frequency to bandwidth ratio.
2. Description of Related Art
Phase locked clocks are well known in the art for generating a local clock which is phase synchronized with an incoming signal or datastream. Typically, a phase comparator compares the incoming signal with the (optionally divided) output of a voltage controlled oscillator (VCO) and generates an error signal (often using a charge pump) which is filtered and used to control the frequency and phase of the VCO so that it phased the locks with the incoming signal.
3. The Problems
The rising demand for high speed input/output has created an increasingly noisy environment in which phase lock loops (PLL) must function. This noise, typically in the form of supply and substrate noise, tends to cause the output of PLLs to jitter from their ideal timing. With a shrinking tolerance for jitter in the decreasing period of the output clock, the design of low jitter PLLs has become very challenging.
Achieving low jitter in PLL designs can be difficult due to a number of design tradeoffs. Consider a typical PLL which is based on a VCO. The amount of input tracking jitter produced as a result of supply and substrate noise is directly related to how quickly the PLL can correct the output frequency. To reduce the jitter, the loop bandwidth should be set as high as possible. Unfortunately, the loop bandwidth is effected by many process technology factors and is constrained to be well below the lowest operating frequency for stability. These constraints can cause the PLL to have a narrow operating frequency range and poor jitter performance.
One solution for these problems was proposed in an article by John G. Maneatis entitled “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques” found in Vol. 31, No. 11, of the IEEE Journal of Solid-State Circuits (November, 1996). That article is hereby incorporated by reference in its entirety and is attached as an appendix to this disclosure.
In phase locked loops which are commonly used for clock recovery and generation in digital systems, a charge pump produces an error current, proportional to phase error, which is passed on to a lowpass filter in order to create a control voltage for a voltage controlled oscillator. It is well-known that a lowpass filter constructed out of a series resistor and capacitor has a desirable property of giving phase margins to promote stability in the closed loop response.
Maneatis and others have noted that a desirable way of constructing a phase locked loop such that the loop's zero (which is the series R-C time constant of the loop filter) is a constant fraction of the loop's bandwidth is to construct the resistance such that it is proportional to the inversed square root of the charge pump's biased current. This constant ratio property is desirable since it implies that the phase margin for the closed loop response will be constant.
The prior art has proposed implementations which use a duplicate error current that is fed onto the output stage of the voltage controlled oscillator biasing circuit, utilizing that circuit's output resistance as the loop resistance. The problem with this approach is that the additional charge pump presents additional loading to the phase detectors which are typically right at the outputs of the first input amplifier (since the closed loop delay must be minimized). Thus, the extra loading results in a performance degradation on the bandwidth of the input stage.
Thus a serious problem exists as to how to create a loop filter in which the resistance is such that it is proportional to the inverse square root of the charge pump's biased current without incurring the deleterious loading on high speed nodes.
SUMMARY OF THE INVENTION
The present invention uses a simple feedback loop entirely contained in the lowpass filter itself to implement and control the loop resistance. The lowpass filter has access to the control voltage V
ctl
that is stored on the loop capacitor. The simple feedback loop consists of an op-amp pulling down on two series connected pmos diodes. The voltage at the drain of the first pmos transistor is compared to V
ctl
and equalized by the closed loop action of the op-amp feedback. The lower pmos diode then transfers an identical voltage across its drain to source. The drain voltage on the lower pmos is used as the gate voltage for the pmos transistors that are placed in series with loop capacitor to implement the loop resistance. The gate to source/drain voltage of these pmos transistors is thus equal to the control voltage of the loop and has a desired property of being proportional to the inverse square root of the biased current. No additional loading has been put on any circuit nodes outside of the loop filter. The loop filter capacitor node can easily handle the extra loading of the control loops since it is specifically targeted to be a heavy capacitance load.
The foregoing and other features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5416438 (1995-05-01), Shibata
patent: 5767714 (1998-06-01), Kotani et al.
patent: 361087409 (1986-05-01), None
Chih-Kong Ken Kang et al., “A 0.8-&mgr;m CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links”, IEEE Journal of Solid-State Circuits, vol. 31, No. 12, Dec. 1996, pp. 2015-2023.
John G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, IEEE Journal of Solid-State Circuits, vol. 31, No. 11, Nov. 1996, pp. 1723-1732.
Ilya Novof et al., “TA 6.5: Fully-Integrated CMOS Phase-Locked Loop with 15 to 240MHz Locking Range and ±50ps Jitter”, 1995 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, ISSCC95/Session 6/Digital Design Elements, Feb. 16, 1995, pp. 112-113.
Bosnyak Robert J.
Cruz Jose M.
Drost Robert J.
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