Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2005-01-04
2005-01-04
Kang, Donghee (Department: 2811)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S025000, C438S026000, C438S107000, C257S686000, C257S777000, C257S778000
Reexamination Certificate
active
06838317
ABSTRACT:
The present invention provides a technique for manufacturing a low cost device that provides a true die to external fiber optic connection. Specifically, the present invention relates to several techniques for joining an optical device package to a semiconductor device package. The first technique involves using wirebond studs and an adhesive material, the second technique involves the use of an anisotropic conductive film, and the third technique involves the use of solder material. Each of these techniques provides high levels of thermal, electrical and optical performance. The methods apply to optical sub-assembly and chip sub-assembly interfaces in transceivers, transmitters, as well as receivers for opto-electronic packages.
REFERENCES:
patent: 5011246 (1991-04-01), Corradetti et al.
patent: 5019673 (1991-05-01), Juskey et al.
patent: 5139969 (1992-08-01), Mori
patent: 5352926 (1994-10-01), Andrews
patent: 5487124 (1996-01-01), Bowen et al.
patent: 5579208 (1996-11-01), Honda et al.
patent: 5608262 (1997-03-01), Degani et al.
patent: 5723369 (1998-03-01), Barber
patent: 5790384 (1998-08-01), Ahmad et al.
patent: 5798567 (1998-08-01), Kelly et al.
patent: 5949135 (1999-09-01), Washida et al.
patent: 6043430 (2000-03-01), Chun
patent: 6201704 (2001-03-01), Poplawski et al.
patent: 6236109 (2001-05-01), Hsuan et al.
patent: 6258630 (2001-07-01), Kawahara
patent: 6305848 (2001-10-01), Gregory
patent: 6316837 (2001-11-01), Song
patent: 6316838 (2001-11-01), Ozawa et al.
patent: 6318909 (2001-11-01), Giboney et al.
patent: 20010013645 (2001-08-01), King et al.
patent: 20010019173 (2001-09-01), Taguchi et al.
patent: 20010048151 (2001-12-01), Chun
patent: 20020047216 (2002-04-01), Jiang et al.
patent: 20020089067 (2002-07-01), Crane et al.
patent: 20020100974 (2002-08-01), Uchiyama
patent: 60-202956 (1985-10-01), None
patent: 08-125066 (1996-05-01), None
S. Savastiouk, PH.D., et al. “3-D stacked wafer-level packaging”, Mar. 2000,Advanced Packaging, pp. 28-34.
National Semiconductor, “Packaging Databook”,1993 National Semiconductor, pp. v-xi to 1-3 to 1-4, 3-1 to 3-20, 3-30 to 3-31, 3-62 to 3-69. Please note: The year of publication is sufficiently earlier than the effective U.S. filing date so that the particular month of publication is not in issue.
Deane Peter
Liu Jia
Mazotti William Paul
Nguyen Luu Thanh
Pham Ken
Kang Donghee
National Semiconductor Corporation
LandOfFree
Techniques for joining an opto-electronic module to a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Techniques for joining an opto-electronic module to a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Techniques for joining an opto-electronic module to a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3397600