Incremental printing of symbolic information – Ink jet – Controller
Reexamination Certificate
2000-07-19
2001-12-04
Barlow, John (Department: 2853)
Incremental printing of symbolic information
Ink jet
Controller
C347S014000
Reexamination Certificate
active
06325483
ABSTRACT:
TECHINICAL FIELD OF THE INVENTION
This invention relates to ink-jet printing, and more particularly to techniques for providing pen identification information.
BACKGROUND OF THE INVENTION
Identification bits are useful in an ink-jet pen, e.g. a thermal ink-jet pen, to identify the pen model, ink color, ink fill and other parameters. Electrical interconnects are used to read this identification from the standard pen electrical interface. The number of interconnections is limited by cost and available space on the printhead die.
The typical technique for encoding information is illustrated in
FIG. 1
, and uses a single low resistance connection or link
12
A-
12
N for each printhead address bit A(O), A(
1
). . . A(N), connecting each address select transistor
10
A,
10
B . . .
10
N to a common “sense” line
14
through a resistance
16
A,
16
B . . .
16
N. Information is stored by connecting or not connecting each of these links
12
A-
12
N. Since there are only two possible states for this link, the number of possible states is 2
N
possible states. The information is read by a resistance measurement on the sense line.
It would be an advantage to be able to store and access more information per interconnect than is provided by existing techniques.
SUMMARY OF THE INVENTION
In accordance with an aspect of the invention, multiple links with series resistors are connected to address select transistors and a sense line in a printhead encoding circuit. In an exemplary embodiment, this arrangement provides 2
(#links×N address lines)
possible states.
In an exemplary embodiment, the printhead data encoding circuit includes a sense line, and a plurality of addressable circuits connected between the sense line and a common connection or reference voltage, such as ground. Each addressable circuit includes a select device and a parallel connection of a plurality of link elements and corresponding resistive elements. Information is encoded by connecting or not connecting the link elements to affect the resistance through the parallel connection.
REFERENCES:
patent: 4872027 (1989-10-01), Buskirk et al.
patent: 5363134 (1994-11-01), Barbehenn et al.
patent: 5504507 (1996-04-01), Watrobski et al.
patent: 5699091 (1997-12-01), Bullock et al.
patent: 5831649 (1998-11-01), Watrobski et al.
Harbour Robert
Shepherd Matthew A.
Barlow John
Hewlett--Packard Company
Stewart Jr. Charles W.
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