Techniques for generating and simulating a simulatable...

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C702S124000

Reexamination Certificate

active

08032350

ABSTRACT:
Methods for generating realistic waveform vectors with controllable amplitude noise and timing jitter, simulatable in a computer-based simulation environment are disclosed. In one implementation, a transition vector is created from a sequence of bits having a rise time and a fall time, in which the transition vector comprises voltage values at timings corresponding to midpoints of transitions in the bit sequence. A jittered transition vector is created from the transition vector, in which the timing of the transitions in the jittered transition vector include timing jitter. An upscaled jittered transition vector is then formed having additional points, in which at least some of the additional points comprise corners of the sequence of bits. The voltages of the additional points are set by the sequence of bits, and the timing of the corners are set in accordance with the rise time and the fall time. Although this resulting vector can be simulated, this vector can also be re-sampled to produce a new simulatable vector in which the voltages are separated by a constant time step.

REFERENCES:
patent: 5682336 (1997-10-01), Chian et al.
McCorquodale et al. Study and Simulation of CMOS LC Oscillator Phase Noise and Jitter. [online] 2003 [retrieved on Dec. 11, 2009] IEEE Database.
Berners, Dave. Ask the Doctors: Resampling Issues. [online] Sep. 2005. [retrieved on Dec. 11, 2009].
U.S. Appl. No. 11/549,646, filed Oct. 14, 2006, Hollis.
U.S. Appl. No. 11/738,193, filed Apr. 20, 2007, Hollis.
Documentation for PRBSsrc (Psuedo-Random Bit Sequence Source) for Agilent Technologies' Advanced Design System (ADS)™, as accessed on Oct. 8, 2007.
Documentation for ClockWjitter (Voltage Source: Clock with Jitter) for Agilent Technologies' Advanced Design System (ADS)™, as accessed on Oct. 8, 2007.
“Clock Source with Random Jitter,” HSPICE RF User Guide Z-2007.03.
Documentation for SynaptiCAD's Waveformer™ module, as downloaded from http://www.syncad.com/syn—time—analysis.htm#clock as downloaded Oct. 8, 2007.
Tektronix, “Controlled Jitter Generation for Jitter Tolerance and Jitter Transfer Testing”, Appl. Note 61W-18431-3, 2005. (C& from original app).
K. K. Kim et al., “On the modeling and analysis of jitter in ATE using Matlab,” in Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, p. 285-93 (Oct. 2005).
S. Tabatabaei et al., “Jitter generation and measurement for test of multi-Gbps serial IO,” in Proceedings of the ITC International Test Conference, pp. 1313-1321 (Oct. 2004).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Techniques for generating and simulating a simulatable... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Techniques for generating and simulating a simulatable..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Techniques for generating and simulating a simulatable... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4292702

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.