Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-05-29
2002-09-24
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185220
Reexamination Certificate
active
06456537
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory devices and, more particularly, to an improved method and apparatus for erasing erasable programmable read-only memory devices (EPROMs).
2. Description of the Related Art
Erasable programmable read only memory (EPROM), electronically erasable programmable read only memory (EEPROM) and flash memory, in particular, are a growing class of non-volatile storage integrated circuits based on floating gate transistors. The memory cells in a flash device are formed using so called floating gate transistors in which the data is stored in a cell by charging or discharging the floating gate. The floating gate is a conductive material, typically polysilicon, which is insulated from the channel of the transistor by a thin layer of oxide, or other insulating material, and insulated from the control gate of the transistor by a second layer of insulating material.
The acts of charging and discharging the floating gate in a floating gate memory device are relatively slow compared to writing other memory types, like static or dynamic random access memory, and limit the speed with which data may be written into the device.
Two different methods of using Fowler-Nordheim tunneling are used to erase a memory cell. In channel, or substrate erase, a positive bias of about 10.0 volts is applied to the substrate of the memory cell. Similarly, a negative bias of about −5.0 volts is applied to the gate of the memory cell. Electron tunneling from the gate to the substrate then erases the memory cell by reducing the charged stored in the floating gate. Channel erase typically requires source isolation by what is referred to as a triple well process which is time consuming, complicated, and expensive. In addition, the time to erase the memory cell using the channel erase procedure is slow since the electric field across the tunnel oxide is reduced due to the low charge carrier concentration in the channel.
Source erase is similar to channel erase except that a positive bias of about 5.0 volts is applied to the source of the memory cell while a negative bias of about −10 volts is applied to the gate of the memory cell. Since source erase does not require source isolation by the triple well process it is simpler and less expensive to implement than is channel erase.
Unfortunately, however, source diode leakage during the source erase procedure lengthens the time require to fully erase an EPROM thereby degrading performance. As well known in the art, several mechanisms have been identified as contributing to the overall performance degradation caused by source diode leakage. One such mechanism is thermal leakage inherent in any tunneling process. Another is referred to as avalanche multiplication, which is electric field dependent and can become quite large if the memory cell is not properly optimized during its fabrication. A third mechanism referred to as band to band tunneling leakage is a fundamental problem with source erase and is discussed by C. Chang et al., Tech. Digest IEDM, 714, 1987 and H. Kume et al., Tech Digest IEDM, 560, 1987 each of which is incorporated by reference in its entirety.
Therefore, what is desired is an improved technique for erasing a floating gate type memory cell, such as an EPROM.
SUMMARY OF THE INVENTION
In a floating gate type semiconductor memory device such as an EPROM or a Flash EPROM, a floating gate in a floating gate transistor is erased by removing a charge stored therein. In one embodiment, the charge is removed by applying a drain potential to a drain node of a selected memory cell having a first polarity concurrently with applying a gate potential to the gate of the selected memory cell having a second polarity. The drain potential and the gate potential are maintained until the charge has been removed from the floating gate structure of the selected memory cell as determined by a verification protocol.
In those cases where the charge is a negative charge, the first polarity is negative and the second polarity is positive.
In another aspect of the invention, a source potential is applied to a source node of the selected memory cell having the first polarity concurrently with applying the gate and the drain potential. The source polarity is maintained until the charge has been removed from the floating gate structure of the selected memory cell as determined by the verification protocol.
In yet another aspect of the invention, a system for erasing a memory cell is disclosed. The memory cell having a gate node coupled to a gate structure, a source node coupled to a source structure, a drain node coupled to a drain structure, wherein a floating gate structure is disposed between the gate structure and the source structure and the drain structure such that a charge is stored in the floating gate structure when the memory cell is programmed and wherein the charged is removed from the floating gate structure when the memory cell is erased. The system includes an address selector unit arranged to select the memory cell and a first potential generator coupled to the memory cell suitably arranged to apply a drain potential to the drain node of the selected memory cell having a first polarity. The system also includes a second potential generator coupled to the memory cell and in communication with the first potential generator arranged to concurrently with the first potential generator to apply a gate potential to the gate of the selected memory cell having a second polarity. The system further includes a verifier unit arranged to verify that the memory cell has been erased such that the first potential generator and the second potential generator maintain the drain potential and the gate potential at their respective potentials until the charge has been removed from the floating gate structure of the selected memory cell as determined by a verification protocol.
REFERENCES:
patent: 4884239 (1989-11-01), Ono et al.
patent: 5650964 (1997-07-01), Chen et al.
patent: 5751636 (1998-05-01), Naruke et al.
patent: 5933367 (1999-08-01), Matsuo et al.
Alliance Semiconductor
Beyer Weaver & Thomas LLP
Mai Son
LandOfFree
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