Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
1999-05-28
2001-03-13
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
Reexamination Certificate
active
06201492
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to analog to digital signal conversion techniques and more particularly to use of pointers to configure channels being converted.
BACKGROUND OF THE INVENTION
Techniques for sampling an analog signal, converting the sampled signal to digital and processing that signal using digital techniques are known in the art. An example of an analog signal source is that provided by a measurement sensor, such as a thermocouple or a strain gauge. Some techniques for sampling an analog signal use a rough buffer to precharge the sampling capacitor followed by a period of fine adjustment. The sampled analog signal is converted to digital. Conversion to digital may produce a digital stream of one or more bits.
Filters for doing such processing, such as FIR filters and FIR sinc filters are known. Some such filters use coefficients for multiplying digital values. Others, such as Hogenauer filters, described in an article by Eugene B. Hogenauer, entitled “AN ECONOMICAL CLASS OF DIGITAL FILTERS FOR DECIMATION AND INTERPOLATION,” published in IEEE Transactions on Acoustics, Speech and Signal Processing, Volume ASSP-29, No. 2, April 1981, perform the filtering without coefficients.
Digital filters such as sinc filters can be implemented using digital circuits for performing a variety of mathematical operation. Multipliers are known which use 2's complement addition to perform multiplication. However, such multipliers require a fair amount of power, machine cycles and silicon real estate to implement.
Some signal processing circuits handle a plurality of channels. Parameters for one or more of such channels may be adjusted using gain and offset registers dedicated for that channel. Some measurement circuits such as those used for weigh scales require an adjustment so that a maximum digital output level corresponds to a calibrated full scale input signal value.
Some integrated circuits use signal processing circuits that can be programmed to set selectable characteristics, such as sampling rate and maximum input voltage. These properties are selected by issuing command signals that are applied to terminals connected to the circuit. Typically, such commands are issued to the circuit every time one of the selectable properties changes. During operation, the number and complexity of such commands issued can become significant.
It would be desirable to have a programmable analog to digital converter (ADC) which could handle a plurality of channels in a flexible way so that high volume conversion can be sustained. It would be further desirable for this flexibility to extend to sampling and converting a plurality of channels in any order, including more repetitions of one channel than another, the ability to sample the same channel at different times with different conversion characteristics, and the ability to skip converting some channels altogether. It would be particularly desirable if conversion properties could be selected flexibility and changed rapidly using fewer and simpler commands than in other signal processing circuits.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide techniques to change combinations of physical channels and conversion properties during operation using a serial port simply and efficiently.
One aspect of the invention relates to a protocol for setting operating parameters for an analog to digital converter (ADC) circuit. The analog signals are converted to digital signals using a device having programmable ADC components that respond to signals indicative of conversion information over a serial port interface. Before operation begins, register content bits may be sent to the device on a serial input pin of the serial port interface. The register content bits include specifications for one or more logical channels. Each logical channel specifies one physical channel with which it is associated and a value for at least one variable ADC property. A plurality of commands can be sent on the serial input pin. Commands can indicate whether data conversion or channel calibration is to be performed. Each command also specifies a logical channel. Conversion or calibration is performed on the physical channel specified in the selected logical channel using the converter property or properties specified in that logical channel. This way a plurality of combinations of physical channel and conversion information can be specified indirectly, using relatively few pointer bits in the command, pointing to the information stored in the logical channel register. Thus, reconfiguration of ADC properties for a particular channel can be made smaller, simpler and faster than by rewriting a full set of properties for a channel through the serial port.
It is an object of the present invention to provide techniques for continuously converting multiple physical channels in an arbitrary order.
In one aspect of the invention, a protocol permits continuously converting analog time-varying signals on selectable channels of a plurality of physical channels. The protocol also permits a single channel to be converted using a plurality of different setups. The analog signals are converted to digital signals using a device having programmable ADC components that respond to signals indicative of some conversion information, a serial port interface, and a serial port controller. Before continuous conversion, register content bits are sent to the device on a serial input pin of the serial port interface. The register content bits include at least one logical channel and a looping bit. Each logical channel specifies one physical channel and a value for at least one variable converter property. Afterwards, commands can be sent on the serial input pin. Each command indicates whether data conversion is to be performed. Each command also selects a logical channel. Then, based on the looping bit, continuous conversion is performed on the physical channel specified in the selected logical channel using the converter property or properties specified in that logical channel. The serial port returns a plurality of scans in succession. Each scan includes one data word for one digital sample from the indirectly selected physical channel and may contain other information. This way a large number of successive data conversions can be performed on a unique combination of physical channel and conversion information using relatively few bits in a single command. The command need not be repeated for every conversion made.
In another aspect of the invention, a protocol permits one to continuously convert analog time-varying signals on selectable multiple channels of a plurality of physical channels. Register content bits are sent over a serial input pin of the serial port interface before issuing any commands. The register content bits include at least one looping bit and a depth of logical channels in the sequence of logical channels in each data scan. The register content bits also include a plurality of logical channels, each specifying one physical channel and conversion information. Then, command bits are sent to the serial input pin. The command bits indicate whether data conversion is to be performed. After this command is issued, a plurality of data scans are received on a serial output pin of the serial port interface. Each data scan includes a number of data words equal to the depth of the logical channel sequence. Each data word provides one digital sample of an analog signal from the physical channel using the converter property indicated by a selected logical channel in the sequence.
In another embodiment, the order of conversion of the logical channels in the sequence is the order those logical channels are stored in the registers of the serial port controller.
REFERENCES:
patent: 5619201 (1997-04-01), Imakura
patent: 5784020 (1998-07-01), Inoue
Hogenauer, Eugene B. “An Economical Class of Digital Filters for Decimation and Interpolation,”IEEE Transactions on Acoustics, Speech and Signal Processing, vol. ASSP.29, No. 2, Apr. 1981, pp. 155-162.
Amar Aryesh
Del Signore Bruce Philip
Cirrus Logic Inc.
Rutkowski Peter
Stewart David L.
Violette J. P.
Young Brian
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