Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2007-05-15
2007-05-15
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C326S030000
Reexamination Certificate
active
11040343
ABSTRACT:
Techniques are provided for controlling an on-chip termination resistance in an input or output (IO) buffer using a calibration circuit. The calibration circuit monitors the voltage between an external resistor and a group of on-chip transistors. When voltage between the external resistor and the group of transistors is within a selected range, the calibration circuit causes the effective resistance of the transistors to match the resistance of the external resistor as closely as possible. The calibration circuit enables another set of transistors in the IO buffer so that the effective on resistance of the transistors in the IO buffer closely match the resistance of the external resistor.
REFERENCES:
patent: 4719369 (1988-01-01), Asano et al.
patent: 4954729 (1990-09-01), Urai
patent: 5111081 (1992-05-01), Atallah
patent: 5134311 (1992-07-01), Biber et al.
patent: 5164663 (1992-11-01), Alcorn
patent: 5179300 (1993-01-01), Rolandi et al.
patent: 5359235 (1994-10-01), Coyle et al.
patent: 5374861 (1994-12-01), Kubista
patent: 5592510 (1997-01-01), Van Brunt et al.
patent: 5602494 (1997-02-01), Sundstrom
patent: 5623216 (1997-04-01), Penza et al.
patent: 5656953 (1997-08-01), Whetsel
patent: 5726582 (1998-03-01), Hedberg
patent: 5726583 (1998-03-01), Kaplinsky
patent: 5764080 (1998-06-01), Huang et al.
patent: 5864715 (1999-01-01), Zani et al.
patent: 5939896 (1999-08-01), Hedberg
patent: 5955911 (1999-09-01), Drost et al.
patent: 5970255 (1999-10-01), Tran et al.
patent: 6008665 (1999-12-01), Kalb et al.
patent: 6020760 (2000-02-01), Sample et al.
patent: 6026456 (2000-02-01), Ilkbahar
patent: 6037798 (2000-03-01), Hedberg
patent: 6049255 (2000-04-01), Hagberg et al.
patent: 6064224 (2000-05-01), Esch, Jr. et al.
patent: 6087847 (2000-07-01), Mooney et al.
patent: 6097208 (2000-08-01), Okajima et al.
patent: 6100713 (2000-08-01), Kalb et al.
patent: 6118310 (2000-09-01), Esch
patent: 6147520 (2000-11-01), Kothandaraman et al.
patent: 6154060 (2000-11-01), Morriss
patent: 6157206 (2000-12-01), Taylor et al.
patent: 6181157 (2001-01-01), Fiedler
patent: 6236231 (2001-05-01), Nguyen
patent: 6252419 (2001-06-01), Sung et al.
patent: 6307791 (2001-10-01), Otsuka et al.
patent: 6329836 (2001-12-01), Drost et al.
patent: 6356106 (2002-03-01), Greeff et al.
patent: 6362644 (2002-03-01), Jeffrey et al.
patent: 6366128 (2002-04-01), Ghia et al.
patent: 6411126 (2002-06-01), Tinsley et al.
patent: 6414512 (2002-07-01), Moyer
patent: 6424169 (2002-07-01), Partow et al.
patent: 6433579 (2002-08-01), Wang et al.
patent: 6445245 (2002-09-01), Schultz et al.
patent: 6448813 (2002-09-01), Garlepp et al.
patent: 6456124 (2002-09-01), Lee et al.
patent: 6466063 (2002-10-01), Chen
patent: 6489837 (2002-12-01), Schultz et al.
patent: 6504397 (2003-01-01), Hart et al.
patent: 6549036 (2003-04-01), Lee
patent: 6570402 (2003-05-01), Koo et al.
patent: 6586964 (2003-07-01), Kent et al.
patent: 6590413 (2003-07-01), Yang
patent: 6603329 (2003-08-01), Wang et al.
patent: 6605958 (2003-08-01), Bergman et al.
patent: 6636821 (2003-10-01), Lawson
patent: 6639397 (2003-10-01), Roth et al.
patent: 6642741 (2003-11-01), Metz et al.
patent: 6700823 (2004-03-01), Rahman et al.
patent: 6710618 (2004-03-01), Murray
patent: 6747475 (2004-06-01), Yuffe et al.
patent: 6766155 (2004-07-01), Salcido et al.
patent: 6788101 (2004-09-01), Rahman
patent: 6947336 (2005-09-01), Kim et al.
patent: 2002/0010853 (2002-01-01), Trimberger et al.
patent: 2002/0060602 (2002-05-01), Ghia et al.
patent: 2002/0101278 (2002-08-01), Schultz et al.
patent: 2003/0062922 (2003-04-01), Douglass et al.
patent: 2004/0008054 (2004-01-01), Lesea et al.
“Apex 20K Programmable Logic Device Family ver. 3.7,” product data sheet Altera Corporation, San Jose, CA (May 2001).
“Apex II Programmable Logic Device Family ver. 1.1,” product Data Sheet, Altera Corporation San Jose, CA (May 2001).
Bendak et al. “CMOS VLSI Implementation of Gigabyte/second computer network links,” proceedings of the 1996 IEEE International Symposium on Circuits and Systems 2:269-272 (May 1996).
Boni et al. “LVDS I/O Interface for Gb/s-per-Pin Operation in 0.35-um CMOS,” IEEE Journal of Solid-State Circuits 36(4):706-711 (Apr. 2001).
Esch et al. “Theory and Design of CMOS HSTL I/O Pads,” The Hewlett Packard Journal, pp. 46-52 (Aug. 1998).
“Spartan-3 1.2V FPGA Family: Functional Description, CA DS099-2 (v1.2),” product specifications Xilinx, Inc., San Jose (Jul. 11, 2003).
“Virtex-II 1.5V Field Programmable Gate Arrays, DSO3102 (v1.5),” product specifications Xilinx, Inc., San Jose, CA (Apr. 2, 2001).
“Virtex-II Platform FPGAs: Detailed Description, DS031-2 (v3.1),” product specifications Xilinx, Inc., San Jose, CA (Oct. 14, 2003).
“Virtex-II Pro Platform FPGAs: Functional Description, DS083-2 (v2.9),” product specifications Xilinx, Inc., San Jose, CA, (Oct. 14, 2003).
Chang Tzung-Chin
Kim Henry
Nguyen Khai Q.
Rangan Gopinath
Sung Chiakang
Altera Corporation
Townsend and Townsend / and Crew LLP
LandOfFree
Techniques for controlling on-chip termination resistance... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Techniques for controlling on-chip termination resistance..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Techniques for controlling on-chip termination resistance... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3774437