Techniques for compensating delays in clock signals on...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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C327S146000, C327S147000, C327S155000, C327S163000

Reexamination Certificate

active

07619451

ABSTRACT:
Techniques are provided for compensating for phase and timing delays in clock signals generated by phase-locked loops and delay-locked loops on integrated circuits. Circuit elements coupled in a feedback loop of a locked circuit can compensate for the timing and phase delays between an input pin and an output pin. Other circuit elements coupled in the feedback loop of a locked circuit can compensate for the delay between an input pin and a destination circuit element. Still other circuit elements coupled in an input reference path of a locked circuit preserve a timing relationship between input clock and input data signals. A clock signal and a data signal received at a destination circuit element have the same phase and timing relationship that exists between the input clock and input data signals at input pins.

REFERENCES:
patent: 6140854 (2000-10-01), Coddington et al.
patent: 6194930 (2001-02-01), Matsuzaki et al.
patent: 6259288 (2001-07-01), Nishimura
patent: 6791381 (2004-09-01), Stubbs et al.
patent: 7071743 (2006-07-01), Starr
patent: 7098707 (2006-08-01), Starr et al.
patent: 7248091 (2007-07-01), Chung
patent: 7471130 (2008-12-01), Gomm et al.
patent: 2005/0242850 (2005-11-01), Kawasaki
patent: 2006/0044033 (2006-03-01), Kim
“PLLs in Sratix II & Stratix II GX Devices,” Altera Corporation, Dec. 2005, pp. 5-1, 5-7, 5-15, 5-19 thru 5-24.

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