Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-06-05
2003-04-22
Tsai, Jey (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S530000, C257S257000, C257S910000
Reexamination Certificate
active
06552409
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of digital memory circuits, and in particular to fabrication techniques for addressing and sensing circuitry for accessing memory elements in a cross-point diode memory arrays.
BACKGROUND OF THE INVENTION
Many consumer devices are now constructed to generate and/or utilize digital data in increasingly large quantities. Portable digital cameras for still and/or moving pictures, for example, generate large amounts of digital data representing images. Each digital image may require up to several megabytes (MB) of data storage, and such storage must be available in the camera. To provide for this type of data storage application, the storage memory should be relatively low in cost for sufficient capacities of around 10 MB to 1 gigabyte (GB). The storage memory should also be low in power consumption (e.g. <<1 Watt) and have relatively rugged physical characteristics to cope with the portable battery powered operating environment. For archival storage, data need only be written to the memory once.
One suitable form of archival storage is described in co-pending U.S. patent application Ser. No. 09/875,356, entitled “Non-Volatile Memory”, the disclosure of which is hereby incorporated herein by reference. The memory system disclosed therein provides high capacity write-once memory at low cost for archival storage. This is realized in part by avoiding silicon substrates, minimizing process complexity and lowering areal density. The memory system includes a memory module formed of a laminated stack of integrated circuit layers constructed on plastic substrates. Each layer contains cross-point diode memory array, and sensing of the data stored in the array is carried out from a separate integrated circuit remotely from the memory module. In order to address, read from and write to all of the memory elements in the arrays of the various memory module layers, a multiplexing scheme is required to avoid having too many interconnections between the memory module and the remote sensing circuitry.
In conventional integrated circuits multiplexing is accomplished by logic gates synthesized from transistors. It is undesirable to include transistors in a diode based cross-point memory array because they will add to the required processing thereby increasing the fabrication cost. Some of the additional processing may be incompatible with other materials used in the cross-point array. If plastic substrates or organic semiconductors are used to form the cross-point memory array, for example, they may be destroyed by temperatures required for transistor fabrication, or they could be damaged by certain solvents used in a wet etching process. Recently, researchers at Lawrence Livermore Laboratories have demonstrated the fabrication of thin-film-transistors on a plastic substrate, however the process required is much more complicated, and hence more expensive, than the equivalent process required to fabricate diodes.
Electrostatic micro-relays have been developed for a number of applications including power relays for automotive application, and small signal switching for instrumentation and automatic test equipment. Electrostatic micro-relay systems are described, for example, in Wong, Jo-Ey, et al., “An Electrostatically-actuated MEMS Switch for Power Applications”, (Micro Electro-Mechanical Systems, 2000. MEMS '00. Thirteenth IEEE. 2000), and Zavracky, P. M., et. al., “Micro-mechanical switches fabricated using nickel surface micro-machining”, (Micro-electromechanical Systems, Journal of, 1997.6(1): p3-9). The principle advantages of this technology are low power consumption and simplicity of construction. Switches of this kind could possibly be used for memory address multiplexing circuitry, although the fabrication processing for these devices is still more significant than that required for a diode array, particularly if a low contact resistance is required.
Another address multiplexing possibility, code-word addressing, includes a number of approaches which have been used to minimize the interconnections to a pixelated display. Such systems are described, for example, in the specification of International Patent Application Publication WO 98/44481, and U.S. Pat. No. 5,034,736. In general code word addressing trades off the ratio of addressing lines to array electrodes and the cross-talk between selected and de-selected electrodes. Although these solutions do not offer log-base-2 reduction in interconnect, they may offer better than 10:1 ratio of electrode to address line, while maintaining a 4:1 cross-talk ratio. Although these solutions are simple to implement since they only involve two-level metal and resistor networks, they require a higher number of address lines for a given number of addressed lines than the true multiplexing schemes described previously. A further disadvantage of these schemes is the cross-talk introduced between addressed and non-addressed memory elements, which makes it difficult to read and write a particular memory element.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, there is provided an integrated circuit structure comprising a first conductor layer having first and second conductor lines, and a second conductor layer having a third conductor line in a crossing relationship with the first and second conductor lines. An intermediate layer having at least one semiconductor material is interposed between the first and second conductor layers at least where the third conductor line crosses the first and second conductor lines so as to form first and second circuit elements through the intermediate layer at the respective crossing junctions of the first and second conductor lines with the third conductor line. The geometry of the first, second and/or third conductor lines at the crossing junctions being such that, upon application of a predetermined electrical signal through the first and second circuit connection elements, the first circuit connection element undergoes a permanent substantial change in resistance with respect to the second circuit connection element.
Preferably the geometry of the first, second and/or third conductor lines is constructed such that said predetermined electrical signal effects a greater electrical current density through the first circuit connection than the second circuit connection.
In a preferred form of the invention the geometry of the first, second and/or third conductor lines is constructed such that the width of the second and/or third conductor lines is broadened in the region of the crossing junction thereof as compared to the crossing junction of the first and third conductor lines.
In one form of the invention, following application of said predetermined electrical signal, the first circuit connection element has a substantially higher resistance than the second circuit connection element.
In another form of the invention, following application of said predetermined electrical signal, the first circuit connection element has a substantially lower resistance than the second circuit connection element.
Preferably the circuit connection elements include a diode formed in the intermediate layer.
The present invention also provides a method of forming integrated circuit connection elements. First, second and third conductor lines are formed, the first and second conductor lines crossing the third conductor line separated by a layer having at least one semiconductor material forming first and second circuit connection elements through the layer at the crossing junctions of the respective first and second conductor lines with the third conductor line. The geometry of the first, second and/or third conductor lines at the crossing junctions are controlled so that, upon application of a predetermined electrical signal through the first and second circuit connection elements, the first circuit connection element undergoes a permanent substantial change in resistance with respect to the second circuit connection element.
In
Elder Richard
Taussig Carl
Hewlett-Packard Development Company LP
Tsai Jey
LandOfFree
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