Coded data generation or conversion – Digital code to digital code converters – Serial to parallel
Reexamination Certificate
2000-05-16
2001-09-18
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Serial to parallel
C375S376000
Reexamination Certificate
active
06292116
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the field of high-speed data input schemes for integrated circuits, and in particular to techniques and circuitry for accurately sampling high frequency input data.
In integrated circuits such a microprocessors, memories, ASICs, and programmable logic devices (PLDs), it is desirable to input data at higher speeds. This allows higher performance integrated circuits, which in turn facilitates higher speed networks, such as the internet. One high speed interface scheme, among others, is known as low voltage differential signal (LVDS). LVDS is being used or will be used with many types of integrated circuits including programmable logic integrated circuits. The LVDS interface is especially useful for interfacing with fiber optic systems. Using LVDS, the data is input serially to the integrated circuit at a rate that is typically higher than the rate at which data is input at a regular data input. For example, a typical data input to the integrated circuit runs at about 80 megahertz while the LVDS data rate may be 8 times that rate.
In order to handle the LVDS data rate, the serial stream must be strobed at the appropriate times in order to correctly determine the data bits in stream. The user provides a input clock used to strobe the LVDS data stream. However, because of the high frequency of the LVDS data rate, the “window” where the LVDS data may be successful strobed is, for example, about 1.6 nanoseconds. Therefore, any skew between the input clock and LVDS input may lead to data errors since the wrong data will be strobed into the integrated circuit. This will lead to logic failures. Misalignment of the clock and input data may be caused by one or more of the following factors: PLL jitter, internal register set-up time and hold time, clock duty cycles, clock skew, process, and temperature variations, skew from the customer board design, and other considerations
Therefore, as can be appreciated, there is a need for interface circuitry and techniques for integrated circuits, especially programmable logic integrated circuits, to handle high frequency input data
SUMMARY OF THE INVENTION
The present invention provides techniques and circuitry for handling high frequency input data. The techniques and circuitry take a high-frequency serial input data stream and covert it into parallel form for handling within the integrated circuit. The circuitry ensures the high frequency data is strobed properly by accounting for skew between the high frequency data input and clock input. In an implementation, multiple clock strobes are generated having the same frequency but different phase. A predetermined series of bits is input to the high frequency input into the circuitry for training. One of the multiple clock strobes is selected based on which one correctly determines the bits in the predetermined input data stream. This clock strobe is selected to strobe the high frequency data input for the integrated circuit. In an embodiment, the high frequency data input is an LVDS input of a programmable logic integrated circuit.
In an embodiment, a phase locked loop (PLL) is designed with the ability to generate multiple clock strobes with programmable, small timing differences which is ideal for adjusting clock strobe positions. The “oversampling” technique works in the following way: By sending multiple clocks to the serial-to-parallel converter at the receiver end, if the calibration data stream pattern is known, by observing the registers of the serial-to-parallel converter, the clock strobe positions can be dynamically adjusted for a small increment of skew relatively to incoming data stream. This process can be repeated several times automatically until the correct data stream is fully captured in the serial-to-parallel converter.
In another embodiment, the invention is a programmable logic integrated circuit including a first register connected to a first input and a first clock signal. A second register is connected to the first input and a second clock signal. A multiplexer is connected to outputs of the first and second register. And, a third register is connected to an output of the multiplexer and a third clock signal, where the first and second clock signals are at a first frequency and have different phases, and the third clock signal is at a second frequency, slower than the first frequency.
In a further embodiment, the invention is an integrated circuit including a high frequency data differential input and a clock input, where a data rate at the data input is at least M times a frequency of a clock signal provided at the clock input. A differential input buffer is connected to the high frequency data input providing a single-ended data input. A clock generator circuit is connected to the clock input and generates a first fast clock signal that is at least M times the clock input. A first shift register and second shift register are connected to receive serial data from the single-ended data input, where the first and second shift registers are clocked using a clock having a frequency of the first fast clock signal at different phases. There are a plurality of multiplexers, one for each bit of the first and second shift registers. Each multiplexer is connected to one bit in the first shift register and one bit in the second shift register. A third register is connected to the multiplexers. Each shift register can hold at least M bits.
The invention includes a method of operating a programmable logic integrated circuit including inputting a predetermined stream of bits at a high frequency input and inputting a clock signal at a clock input. From the clock signal, a first and second fast clock signal are generated, each having the same frequency but different phases. The predetermined stream is loaded into a first shift register using the first fast clock signal. The predetermined stream is loaded into a second shift register using the second fast clock signal. Data is selectively passed from the first or second shift register to a third register.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.
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Huang Joseph
Kim In Whan
Nguyen Khai
Sung Chiakang
Wang Bonnie I.
Altera Corporation
Townsend and Townsend / and Crew LLP
Williams Howard L.
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