Technique to reduce ESD loading capacitance

Details Technique to reduce ESD loading capacitance Technique to reduce ESD loading capacitance

2008-01-01

2008-01-01

Sherry, Michael (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

07315438

ABSTRACT:
The capacitive loading effects of an ESD circuit having an electrostatic-protection diode are reduced by using a capacitance compensation circuit. Under normal operation when no electrostatic discharge is experienced, the capacitance reduction circuit maintains a reverse bias across the electrostatic-protection diode, which causes the diode's capacitance to be reduced below a predetermined value. When an electrostatic discharged is experienced, the capacitance compensation circuit removes the applied reverse bias, and shunts the electrostatic-protection diode to a power rail.

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