Technique to increase dynamic range of a CCD image sensor

Details Technique to increase dynamic range of a CCD image sensor Technique to increase dynamic range of a CCD image sensor

1998-12-08

2004-03-16

Garber, Wendy R. (Department: 2612)

Television

Camera, system and detail

Solid-state image sensor

C348S322000, C348S297000, C348S319000, C257S230000, C250S208100

Reexamination Certificate

active

06707499

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of driving a solid-state imaging device and more particularly, to a method of driving a solid-state imaging device to increase the dynamic range of a CD image sensor.
2. Description of the Prior Art
Charge coupling device (CCD) image sensors offer a variety of applications as imaging picking up devices. Examples are the DSC (digital still camera) and video camera used for home-use, industrial and broadcasting purposes. Electric imaging merchandise has drawn much attraction to the improvement in image quality and sensing speed of CCD-related technology, such as the photo-sensing device structure and/or the driving circuit.
FIG. 1
shows a conventional solid-state imaging apparatus that includes a plurality of photo sensors
100
arranged in association with a plurality of vertical CCD registers
200
(herein after called VCCD) in columns. In addition, a row of horizontal CCD registers
300
is disposed and connected with one end of each columns of vertical CCD registers to transfer the signal charges received from those vertical CCD registers to an output circuit member
400
.
The detailed relationship between a photo sensor array and a VCCD is illustrated with an example of a column of the same. Simultaneously referring to FIG.
1
and
FIG. 2A
, a first photo sensor
111
is adjacent to a first VCCD register
211
and a second photo
112
is connected with a third VCCD register
213
on the one side in the horizontal direction. The other side of each photo sensor
100
is adjacent to an isolation region
50
. In the vertical direction, the VCCD register
211
is connected in series adjacent to VCCD registers
212
,
213
,
214
and so on. In addition, the VCCD registers
211
,
212
,
213
, and
214
are connected to electrodes V
1
, V
2
, V
3
and V
4
, respectively. The VCCD registers
215
,
216
,
217
, and
218
are connected with electrodes V
1
, V
2
, V
3
and V
4
, respectively. In other word, the signal charges transferred are carried out by modes of the four phases. Furthermore, the photo sensors
111
,
112
and
113
are treated by complementary color filters so that they receive different signal charges. That is, three adjacent photo sensors constitute a set for representing the original color. For example, the first photo sensor
111
accesses the magenta color signal and the second photo sensor
112
accesses another kind of signal such as cyan. The third photo-sensor
113
accesses the green color signal. The remaining photo sensors of each of columns are arranged in a similar way.
Before picking up each pixel of an image, as shown in
FIG. 2B
, the contents of a photo sensor array
100
must first be reset. A sufficient high reverse voltage level of about 30 V (herein after called V
H
) is applied at a terminal V
SUB
to form a depletion region
35
for each photo sensor. When the depletion regions
35
are expanded to overlap N-regions
40
of the photo sensor array
100
, any charges in the photo sensors
100
are then discharged to the N-SUB
30
. On the other hand, to start picking up an image, the terminal V
SUB
is supplied with a slighter lower level (herein after called V
M
) of reverse bias of about 15 V. At this time, the depletion region
35
is formed and the signal charges in the photo sensors
100
are stored, as shown in FIG.
2
C.
To read out the signal charges from a photo sensor, the electrode V
1
should have a sufficient high voltage applied thereto.
FIG. 2D
shows various depths of the potential wells with respect to the timing and the voltage levels. At a time T
1
, V
1
is at a voltage level “m”, and a depth of the potential well under electrode V
1
at about an “m” level is formed. However, there is nothing to dispose to the VCCD
200
because there is a potential barrier to prevent the charge signal blooming. At a time T
2
, the corresponding potential decreases, and the height of the potential barriers increases. To read out the signal charges in a photo sensor, at a time of T
3
, the potential barrier disappears in response to a voltage level “h” supplied at electrode V
1
. A deep potential well is formed under the electrode V
1
regions so that the signal charges are disposed thereto.
Referring to
FIG. 3A
, a waveform diagram showing the timings with respect to various pluses is given to illustrate a conventional method of driving the solid-state imaging device shown in
FIGS. 1-2
. The V
SUB
, is pulsed with a high voltage of about V
H
to reset the photo sensors
100
firstly, and then supplied with a slightly reverse bias V
M
at the time indicated by “@”. When the photo sensors
100
are exposed to the optical signal, the signal charges can be stored in it. Each of the photo sensors
100
provides an upper limited quantity “Q” of the charge storage capacity, and the charges in the photo sensors
200
are saturated after a period of time Cs. Therefore, to avoid a charge bloom, the vertical blanking signal VBLK is lowered (blanked) to a “0” state prior to saturation of the signal charges in photo sensors
100
. At the same time, the exposure of photo sensors
100
is stopped. Generally, the signal charges in photo sensors
100
are not read out to the VCCD registers.
200
until time “®” in response to reading pulses XSG
1
and XSG
2
. It is noted that the XSG
1
is processed by an inverter (not shown), and then connected to the electrode V
1
. The processed voltage level of the pulse XSG
1
is same as the voltage level “h” indicated in FIG.
2
D. The XSG
2
is similar to the XSG
1
pulse being processed by an inverter (not shown), but the processed voltage of the pulse XSG
2
is then connected to electrode V
3
so as to read out the signal charges in the second photo sensor
112
thereof.
An example of charges transferred by four-phase CCD is shown in FIG.
4
. It is noted that the pulse XV
1
is also processed by an inverter (not shown) and then the processed pulse of XV
1
is applied to the electrode V
1
to form a potential well thereunder. Certainly, as indicated in
FIG. 2D
, the depth of potential well varies with the magnitude of voltage level. The pulses XV
2
, XV
3
, and XV
4
are similar to XV
1
, which are respectively in response to the electrode V
2
, V
3
, and V
4
. At a T
1
time, XV
1
and XV
2
are supplied with a lower voltage. That is, both V
1
and V
2
are in a “high” state. Thus a potential well
201
under electrode XV
1
and XV
2
is formed, and charges Q are stored there. At a time of T
2
, XV
2
remains the same, but XV
1
voltage is increased by half and XV
3
voltage is decreased by half, and thus two shallow potential wells
202
,
203
and a deep potential well
204
are, respectively, formed under the electrodes V
1
, V
3
and V
2
. In other words, a portion of the charges Q is transferred from the region under the electrode XV
1
to that of electrode XV
3
. Similarly, at T
3
time, the XV
1
is raised to a high state (V
1
is at “low state”), and thus the potential well thereunder disappears. The chares Q is then completely transferred from a region under the electrode V
1
to a region under the electrodes V
2
and V
3
, which have a high voltage. Finally, at a time of T
4
all charges Q are adjacently disposed on the right side thereof as shown in
FIG. 4
, and the potential well is formed under electrodes V
3
and V
4
.
Conventional transferal of the signal charges in VCCD using SONY ICX058AK chip is given as an example. It is done by an interlacing manner. As is shown in FIG.
3
A and
FIG. 1
, a sufficient high reverse voltage level of about 30 V (herein after called V
H
) is applied at a terminal V
SUB
to reset all the photo sensors
100
, which are then exposed to the optical light start. The photo sensors
100
receive the signal charges for a period of time Cs. When BLK falls down to a “low” state, the first photo sensor
111
receives Q
11
, a quantity of charges, the second photo sensor
112
receives charges Q
12
, the third photo sensor
113
receives Q
13
, and so on. It is noted

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