Technique to enable store forwarding during long latency...

Details Technique to enable store forwarding during long latency... Technique to enable store forwarding during long latency...

2011-03-01

2011-03-01

Kindred, Alford W (Department: 2181)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

C712S218000, C712S219000

Reexamination Certificate

active

07900023

ABSTRACT:
A technique to allow independent loads to be satisfied during high-latency instruction processing. Embodiments of the invention relate to a technique in which a storage structure is used to hold store operations in program order while independent load instructions are satisfied during a time in which a high-latency instruction is being processed. After the high-latency instruction is processed, the store operations can be restored in program order without searching the storage structure.

REFERENCES:
patent: 5878242 (1999-03-01), Olson et al.
patent: 6021485 (2000-02-01), Feiste et al.
patent: 6675287 (2004-01-01), Gaskins et al.
Baugh et al.; “Decomposing the Load-Store Queue by Function for Power Reduction and Scalability”; 2004.
Office Action received for Chinese Patent Application No. 200510119155.8, mailed on Jun. 22, 2007, 6 pages of Office Action and 8 pages of English Translation.
Office Action received for Chinese Patent Application No. 200510119155.8, mailed on Dec. 14, 2007, 5 pages of Office Action and 8 pages of English Translation.
Office Action received for Chinese Patent Application No. 200510119155.8, mailed on Apr. 18, 2008, 4 pages of Office Action and 6 pages of English Translation.
Office Action received for Chinese Patent Application No. 200510119155.8, mailed on Dec. 18, 2009, 4 pages of Office Action and 6 pages of English Translation.

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