Technique of forming over an irregular surface a polysilicon lay

Details Technique of forming over an irregular surface a polysilicon lay Technique of forming over an irregular surface a polysilicon lay

1994-12-19

1997-01-21

Niebling, John

Fishing, trapping, and vermin destroying

437228, 437233, 437186, H01L 218247

Patent

active

055959245

ABSTRACT:
Techniques of forming a flash EEPROM cell array with the size of individual cells being reduced, thereby increasing the number of cells which may be formed on a semiconductor substrate of a given size. Use of dielectric spacers in several steps of the process controls areas being etched or implanted with ions to something smaller than can be obtained by the highest resolution photolithography. Both split-channel and non-split-channel (no select transistor) types of memory cells are included. Example cells employ three polysilicon layers, having separate floating, control and erase gates. A technique of forming the memory cell gates with greater uniformity of conductivity level includes depositing undoped polysilicon and then using ion implantation to introduce the dopant. Field oxide is formed at an early stage in the process by CVD deposition and dry etching. The memory cell array and adjacent peripheral components are formed in a coordinated manner on a single integrated circuit chip.

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Dong et al., "Method for Fabricating Good Quality Continuous Thin Polycrystalline Silicon Films", IBM Technical Disclosure Bulletin, vol. 22, No. 4, Sep. 1979, p. 1441.

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