Technique for threshold control over edges of devices on silicon

Details Technique for threshold control over edges of devices on silicon Technique for threshold control over edges of devices on silicon

1977-04-04

1978-01-24

Ozaki, G.

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

148 15, 156649, 357 56, H01L 2122

Patent

active

040702111

ABSTRACT:
A self-aligning technique for doping the edges of metal-oxide-semiconductor evices fabricated on silicon-on-sapphire to eliminate channel-edge conduction at voltages lower than the device threshold voltage without unnecessarily doping the top conducting surface of the device. A thick masking layer is deposited on the silicon layer. The masking layer is etched locally to expose the silicon in the regions between the devices and the exposed silicon is etched to form islands on the sapphire substrate. In a new step, a partial etch of the masking layer is conducted to expose a narrow frame on the top surface and edges of the silicon island. The resulting structure may be doped by any conventional method to ensure heavier doping at the edges than in the transistor channel region.

REFERENCES:
patent: 3698966 (1972-10-01), Harris
patent: 3730778 (1973-05-01), Shannon et al.
patent: 3832246 (1974-08-01), Lynch
patent: 3899363 (1975-08-01), Dennard et al.
patent: 3958266 (1976-05-01), Athanas
patent: 3974515 (1976-08-01), Ipri et al.
patent: 3997367 (1976-12-01), Yau
patent: 4002501 (1977-01-01), Tamura

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