Technique for switching between input clocks in a...

Details Technique for switching between input clocks in a... Technique for switching between input clocks in a...

2006-09-29

2008-07-29

Chang, Joseph (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C327S147000

Reexamination Certificate

active

07405628

ABSTRACT:
A technique that is readily implemented in monolithic integrated circuits reduces or eliminates phase glitches when switching between input reference clock signals. The technique combines a pulsed phase-difference signal and a pulsed phase-difference compensation signal to substantially attenuate a DC component of the phase-difference signal and at least partially attenuate harmonic components of the phase-difference signal. The pulsed phase-difference compensation signal is based on an indicator of a phase difference between the input reference clock signals.

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Wei, Derrick C. et al., “A Monolithic Low-Bandwidth Jitter-Cleaning PLL with Hitless Switching for SONET/SDH Clock Generation,” 2006 IEEE International Solid-State Circuits Conference, Session 13.3, Digest of Technical Papers, First Edition, vol. 49, Feb. 2006, pp. 176-177 and 236-237.

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