Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated...
Reexamination Certificate
2011-08-16
2011-08-16
Smith, Bradley K (Department: 2894)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
C257SE21214, C257SE23194, C438S110000
Reexamination Certificate
active
07999348
ABSTRACT:
A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second main surface. The second main surface of the device layer is disposed on a surface of the dielectric layer opposite to the semiconductor substrate. A plurality of intended die areas are defined on the first main surface of the device layer. The plurality of intended die areas are separated from one another. A plurality of die access trenches are formed in the semiconductor substrate from the second main surface. Each of the plurality of die access trenches are disposed generally beneath at least a respective one of the plurality of intended die areas.
REFERENCES:
patent: 4211582 (1980-07-01), Horng et al.
patent: 4238278 (1980-12-01), Antipov
patent: 4491486 (1985-01-01), Iwai
patent: 4866004 (1989-09-01), Fukushima
patent: 4895810 (1990-01-01), Meyer et al.
patent: 4994406 (1991-02-01), Vasquez et al.
patent: 5019522 (1991-05-01), Meyer et al.
patent: 5366914 (1994-11-01), Takahashi et al.
patent: 5432113 (1995-07-01), Tani
patent: 5479048 (1995-12-01), Yallup et al.
patent: 5585285 (1996-12-01), Tang
patent: 5902127 (1999-05-01), Park
patent: 5926713 (1999-07-01), Hause et al.
patent: 6174773 (2001-01-01), Fujishima
patent: 6214698 (2001-04-01), Liaw et al.
patent: 6495421 (2002-12-01), Luo
patent: 6534367 (2003-03-01), Peake et al.
patent: 6613644 (2003-09-01), Lachner
patent: 6762473 (2004-07-01), Goushcha et al.
patent: 6797589 (2004-09-01), Adams et al.
patent: 6940144 (2005-09-01), Nakayama
patent: 7015104 (2006-03-01), Blanchard
patent: 7023069 (2006-04-01), Blanchard
patent: 7041560 (2006-05-01), Hshieh
patent: 7052982 (2006-05-01), Hshieh et al.
patent: 7429772 (2008-09-01), Wilson et al.
patent: 2004/0157410 (2004-08-01), Yamaguchi
patent: 2005/0176192 (2005-08-01), Hshieh
patent: 2006/0079024 (2006-04-01), Akram
patent: 2007/0166997 (2007-07-01), Knorr
patent: 2007/0262378 (2007-11-01), Wilson et al.
patent: 2005001941 (2005-01-01), None
patent: 2005001941 (2005-01-01), None
patent: 2005031880 (2005-04-01), None
U.S. Appl. No. 11/380,457, filed Apr. 27, 2006, Wilson, et al.
U.S. Appl. No. 11/675,407, filed Feb. 15, 2007, Wilson, et al.
Brogan Conor
Griffin Hugh J.
MacNamara Cormac
Wilson Robin
Icemos Technology Ltd.
Panitch Schwarze Belisario & Nadel LLP
Payen Marvin
Smith Bradley K
LandOfFree
Technique for stable processing of thin/fragile substrates does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Technique for stable processing of thin/fragile substrates, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Technique for stable processing of thin/fragile substrates will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2682705