Technique for reducing substrate warpage springback using a poly

Details Technique for reducing substrate warpage springback using a poly Technique for reducing substrate warpage springback using a poly

1984-12-10

1986-12-30

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29580, 148174, 148175, 148DIG25, 148DIG85, 148DIG86, 148DIG135, 148DIG122, 357 49, 427 86, H01L 21304, H01L 21316

Patent

active

046318046

ABSTRACT:
A technique is disclosed for the artificial introduction of a localized subsurface strained layer within a thick polysilicon layer to minimize the large change in warpage (defined as springback) which occurs in a (100) Si substrate thinning operation during the mechanical processing of dielectrically isolated (DI) wafers. This novel technique is capable of favorably altering the state of stress and the stress profile in the multicomponent "polysilicon/SiO.sub.2 /(100) Si" DI structure so as to reduce the natural springback in warpage that occurs when the stiffening member, the (100) Si substrate, is removed. This subsurface disturbed layer is retained within the polysilicon layer during subsequent processing to maintain the favorable stress profile with a minimum of wafer warpage. In one embodiment of the present invention, the subsurface strained layer is generated by growing an interface layer (SiO.sub.2 or Si.sub.3 N.sub.4) onto a first polysilicon layer onto which a second polysilicon layer is deposited to attain the desired thickness. In an alternative embodiment, a polysilicon grind is performed on a first layer and a second polysilicon layer is deposited on this ground surface, where the disturbed layer results from the mechanical grind operation. Alternatively, a subsurface psuedo interface may be formed by a sudden radical change in the growth rate of the actual polysilicon deposition process, where the highly strained and defective layer results from the drastic quench in the polysilicon growth rate.

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