Technique for reducing dishing in Cu-based interconnects

Details Technique for reducing dishing in Cu-based interconnects Technique for reducing dishing in Cu-based interconnects

2000-06-29

2001-11-20

Powell, William A. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C216S038000, C216S041000, C216S088000, C438S745000

Reexamination Certificate

active

06319837

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to reducing dishing in metal interconnects, particularly damascene structure interconnects found in integrated circuit wafers.
BACKGROUND OF THE INVENTION
In the manufacture of integrated circuits, interconnects within a level are made by damascene feature called trenches that are filled with an electrically conductive material like metal. Interconnects between levels are made by damascene features called vias. These interconnects are made by first etching a line, in the case of trenches, or a hole, in the case of vias in a substrate. An electrical conductor is then deposited over the entire substrate. The excess conductor is removed by planarizing the substrate with, for example chemical-mechanical polishing.
Ideally, this process produces an interconnect with a top surface that is co-planar with top surface of the substrate. Unfortunately, since chemical mechanical polishing is an abrasive technique, the differing hardnesses of the interconnect material and the substrate material means that they will have different polishing rates. Since the interconnect material, for example aluminum alloy, is softer than the substrate material, for example silicon dioxide or silicon, the interconnect structure will exhibit “dishing,” which is a concave shaped surface of the interconnect. This is undesirable for two reasons. Firstly, the cross-sectional area of the interconnect is reduced, which reduces the current carrying capability of the interconnect and increases the sheet resistance. Secondly, the increased radius of curvature where the lip of the dish meets the substrate surface of the substrate increases the local electric field, which worsens electromigration. Dishing has become even more of a concern with the introduction of copper to integrated circuit manufacturing, as copper is softer than the aluminum alloys, such as aluminum silicon copper, which had heretofore been used. Dishing is also exacerbated when interconnects are isolated, because the abrasion rate becomes more uniform as the area of softer material presented for abrasion increases. In other words, widely spaced interconnect lines tend to display reduced copper fill after electroplating and subsequent planarization.
SUMMARY OF THE INVENTION
The present invention includes a method for reducing dishing of an integrated circuit interconnect, comprising the steps of providing excess interconnect material above a damascene structure in a substrate and planarizing the substrate and interconnect material to obtain an interconnect in the substrate.


REFERENCES:
patent: 5502008 (1996-03-01), Hayakawa et al.
patent: 5578523 (1996-11-01), Fiordalice et al.
patent: 6083835 (2000-07-01), Shue et al.
patent: 6103625 (2000-08-01), Marcyk et al.

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