Technique for receiving differential multi-PAM signals

Pulse or digital communications – Receivers

Reexamination Certificate

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Details

C375S353000, C375S286000, C375S268000, C375S136000, C327S336000, C327S333000, C327S052000, C327S062000

Reexamination Certificate

active

10673677

ABSTRACT:
A technique for receiving differential multi-PAM signals is disclosed. In one particular exemplary embodiment, the technique may be realized as a differential multi-PAM extractor circuit. In this particular exemplary embodiment, the differential multi-PAM extractor circuit comprises an upper LSB sampler circuit configured to receive a differential multi-PAM input signal and a first differential reference signal, and to generate a first differential sampled output signal. The differential multi-PAM extractor circuit also comprises a lower LSB sampler circuit configured to receive the differential multi-PAM input signal and a second differential reference signal, and to generate a second differential sampled output signal. The differential multi-PAM extractor circuit further comprises a combiner circuit configured to receive the first differential sampled output signal and the second differential sampled output signal, and to generate a differential LSB output signal indicating an LSB value of the differential multi-PAM input signal.

REFERENCES:
patent: 6396329 (2002-05-01), Zerbe
patent: 6462623 (2002-10-01), Horan et al.
patent: 6614371 (2003-09-01), Zhang
patent: 6825696 (2004-11-01), Jaussi et al.
patent: 2002/0091948 (2002-07-01), Werner et al.
patent: 2003/0194016 (2003-10-01), Gorecki et al.
patent: 2004/0119627 (2004-06-01), Jaussi et al.
M. Rau et al., “Clock/Data Recovery PLL Using Half-Frequency Clock,” IEEE Journal Of Solid-State Circuits, vol. 32, No. 7, July 1997, pp. 1156-1159.
Chih-Kong et al., “A 0.8-μm CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Link,” IEEE Journal Of Solid-State Circuits, vol. 31, No. 12 Dec. 1996, pp. 2015-2023.
Ramin Farjad-Rad et al., “A 0.3-μm CMOS 8-Gb/s 4-PAM Serial Link Transceiver,” IEEE Journal Of Solid-State Circuits, vol. 35, No. 5, May 2000, pp. 757-764.
Kun-Yung Ken Chang et al., “A 0.4-4Gb/s CMOS Quad Transceiver Cell using On-chip Regulated Dual-Loop PLLs,” 4 pages, 2002.

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