Technique for providing a sign/magnitude subtraction operation i

Details Technique for providing a sign/magnitude subtraction operation i Technique for providing a sign/magnitude subtraction operation i

1988-09-28

1990-12-18

Harkcom, Gary V.

Boots, shoes, and leggings

364748, G06F 750

Patent

active

049791419

ABSTRACT:
A system for use in a floating point computation unit for providing a sign/magniture subtraction operation, which system uses propagate/generate logic responsive to the subtraction operands to produce intermediate and final propagate and generate outputs. First carry computation logic is responsive to the final propagate and generate outputs and to a carry-in bit to produce final carry outputs and a carry-out bit. The latter outputs are used to produce a first subtraction result. Second carry computation logic responds to the intermediate propagate and generate outputs to produce second final carry outputs. The latter outputs and selected intermediate propagate outputs are used to produce a second subtraction result. The carry-out bit then selects one of the two subtraction results as the final subtraction result.

REFERENCES:
patent: 3814925 (1974-06-01), Spannagel
patent: 4319335 (1982-03-01), Rubinfield
patent: 4811272 (1989-03-01), Wolrich et al.

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