Electricity: electrical systems and devices – Safety and protection of systems and devices – Transient responsive
Reexamination Certificate
2001-01-08
2004-08-31
Huynh, Kim (Department: 2182)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Transient responsive
C361S056000
Reexamination Certificate
active
06785109
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to integrated circuit devices, and more particularly to a technique for protecting such devices against electrostatic discharge (ESD) damage.
As the number of power and/or ground buses within a device increases, achieving effective ESD protection of that device becomes more difficult. Conventional solutions for handling ESD between multiple power and/or ground buses often involve clamping an ESD protection circuit between each combination of power and ground buses. Such exhaustive cross-clamping soon becomes difficult, if not impractical, as the number of power and/or ground buses increases. Similarly, for the input/output (I/O) circuitry, applying conventional ESD protection techniques such as using large I/O transistors and/or providing complex ESD protection circuits for each I/O pad may become unwieldy as the number of power and/or ground buses increases.
SUMMARY OF THE INVENTION
The present invention relates to an improved technique for providing ESD protection for integrated circuit devices with multiple power and/or ground buses. The technique involves clamping each power bus, ground bus, and I/O pad within a device to a respective one of the ground buses. In accordance with the principles of the present invention, this arrangement provides a discharge path between any power bus, ground bus, and I/O pad during an ESD event without resorting to exhaustive cross-clamping. Moreover, this technique simplifies the I/O protection circuitry, thereby saving chip area and decreasing I/O capacitance.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the invention.
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K. Narita, Y. Horiguchi, T. Fujii, and K. Nakamura, “A Novel On-Chip Electrostatic Discharge (ESD) Protection with Common Discharge Line for High-Speed CMOS LSI's”, IEEE Transactions on Electron Devices, vol. 44, No. 7, Jul. 1997, pp. 1124-1130.
Costello John
Huang Cheng H.
Sung Chiakang
Altera Corporation
Fish & Neave
Huynh Kim
Jackson Robert R.
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