Technique for programming floating-gate transistor used in...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185260, C365S185280

Reexamination Certificate

active

07126854

ABSTRACT:
The sequence in which the voltages (VSL, VDL, VSG, and VCL) applied to the source/drain regions (S and D), select gate (SG), and (if present) control gate (CG) of a floating-gate field-effect transistor (20) start to change value during a programming operation is controlled so as to avoid adjusting the transistor's programmable threshold voltage toward a programmed value when the transistor is intended to remain in the erased condition, i.e., not go into the programmed condition. With the voltage (VSL) at one source/drain region (S) changing from a nominal value to a programming value, the sequence entails causing the voltage (SG) at the select gate to start changing from a nominal value to a programming-enable value after the voltage at the other source/drain region (D) starts changing from a nominal value to a programming-inhibit value.

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U.S. Appl. No. 10/640,929, filed Aug. 2003, inventor Kim.
U.S. Appl. No. 10/780,030, filed Feb. 2004, inventor Park.
Nation el al., “Architectural Impacts on Flash Endurance and Flash Data Retention”, AMD Flash Technology White Paper, Rev. 37, Advanced Micro Drives, Nov. 7, 1999, pp. 1 - 17.

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