Technique for preventing forward biased epi-isolation degradatio

Details Technique for preventing forward biased epi-isolation degradatio Technique for preventing forward biased epi-isolation degradatio

1976-10-28

1978-09-12

Rutledge, L. Dewayne

Metal treatment

Compositions

Heat treating

357 20, 357 47, 357 91, H01L 21265

Patent

active

041135121

ABSTRACT:
Certain types of silicon integrated circuits are embodied as having diffused isolation regions surrounding epitaxial regions. Although normally operated in a reverse bias mode, such regions may become forward biased when sourcing current for certain circuit applications. Certain types of ionized impurities lodged in the isolation region can then migrate into the depletion region and the epitaxial region of the device during a forward bias condition. Such contaminants can be expected to produce generation-recombination centers in the depletion layer of the device which, when the isolation region is then reverse biased, will produce significant increases in junction leakage current. The magnitude of this reverse bias leakage current will depend upon both the contaminant concentration and the width of the depletion region.

REFERENCES:
patent: 3551760 (1970-12-01), Tokuyama
patent: 3631311 (1971-12-01), Engbert
patent: 3653988 (1972-04-01), Glinski
patent: 3697827 (1972-10-01), Simon
patent: 3760239 (1973-09-01), Fletcher et al.
patent: 3964705 (1976-06-01), Giovanni
patent: 4021270 (1977-05-01), Hunt et al.
H. H. Berger et al., "Producing Reduced Inverse Beta Transistors", IBM TDB, 14 (1971) 752.

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