Technique for placement of pipelining stages in multi-stage data

Details Technique for placement of pipelining stages in multi-stage data Technique for placement of pipelining stages in multi-stage data

1989-01-13

1992-07-21

Lee, Thomas C.

Boots, shoes, and leggings

395250, 364489, G06F 1531, G06F 938

Patent

active

051330695

ABSTRACT:
According to a method for designating the locations of pipelining stages in multi-stage datapath elements, the delay associated with each stage of the multi-stage element is estimated. Then, beginning with a designated stage of the multi-stage element, the estimated delays for the individual stages are added to obtain an accumulated delay time. Whenever the accumulated delay time exceeds a desired cycle time, a pipelining stage is inserted into the multi-stage element prior to the stage which caused the accumulated delay time to exceed the desired operating cycle time. Then, the method is continued for succeeding stages in the datapath element until all of its stages have been accounted for.

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C. E. Hauck et al., "The Systematic Exploration of Pipelined Array Multiplier Performance," Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing, Tampa, Fla., Mar. 26-29, 1989, pp. 1461-1464.
J. R. Jump et al., "Effective Pipelining of Digital Systems," IEEE Transactions on Computers, vol. C-27, No. 9, Sep. 1978, pp. 855-865.
C. Asato et al., "A Datapath Multiplier with Automatic Insertion of Pipeline Stages," IEEE Proceedings of the Custom Integrated Circuits Conference, San Diego, Calif., May 15-18, 1989.
Jump et al., "Effective Pipeling of digital Systems", IEEE Transactions on Computers, vol. C-27, No. 9 (Sep. 1978), pp. 855-865.

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