Technique for oversampling to reduce jitter

Details Technique for oversampling to reduce jitter Technique for oversampling to reduce jitter

2007-06-19

2007-06-19

Bayard, Emmanuel (Department: 2611)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

Reexamination Certificate

active

10692079

ABSTRACT:
To achieve improved jitter performance within prescribed bandwidth constraints, a receiver (140) samples a digital signal (11) upon each of n periodic sample clock pulses that occur during the interval t, where n is chosen such that log2(n+1) is an integer (x) greater than zero. At the each of each interval t, the receiver generates a x+1-bit sample value having a first bit indicating the value of the digital signal being sampled, and x remaining bits which collectively indicate a sample interval during which the digital signal changed states if such a change did occur When a change does occur, the receiver inverts the first bit of each sample value upon decoding to coincide with the change in the digital signal.

REFERENCES:
patent: 4821297 (1989-04-01), Bergmann et al.
patent: 5400370 (1995-03-01), Guo
patent: 5761254 (1998-06-01), Behrin
patent: 2003/0095619 (2003-05-01), Vallet et al.
Park J-Y et al.: “A 1.0 GBPS CMOS Oversampling Data Recovery Circuit with Fine Delay Generation Method” IEICE Transactions on Fundamental of Electronics, Communications and Computer Sciences, Institute of Electronics Information and Comm. Eng. Toyko, JP, vol. E83-A, No. 6 Jul. 13, 1999 pp. 1100-1105, XP001032162.

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