Fishing – trapping – and vermin destroying
Patent
1990-04-17
1992-03-10
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437192, 437194, 437200, H01L 2190
Patent
active
050949810
ABSTRACT:
Electrical connections to specified semiconductor or electrically conductive portions (18, 26, and 30) of a structure created from a semiconductive body (10) are created by a process in which a titanium contact layer (34) is deposited on the structure over the specified portions. An electrically conductive barrier material layer (36) which consists principally of non-titanium refractory material is formed over the contact layer. The resulting structure is then annealed at a temperature above 550.degree. C. in order to lower the contact resistance. The anneal is preferably done at 600.degree. C. or more for 10-120 seconds in a gas whose principal constituent is nitrogen. An electrically conductive primary interconnect layer is formed over the barrier material layer after which all three layers are patterned to create a composite interconnect layer.
REFERENCES:
patent: 4477310 (1984-10-01), Park et al.
patent: 4782380 (1988-11-01), Shankar et al.
patent: 4829024 (1989-05-01), Klein et al.
patent: 4884123 (1989-11-01), Dixit et al.
patent: 4886764 (1989-12-01), Miller et al.
C. Y. Ting et al, "The Use of Ti-Based Contact Barrier Layers in Silicon Technology", Thin Solid Films, vol. 96 (1982) pp. 327-345.
P. B. Ghate et al, "Application of TiW Barrier Metallization for Integrated Circuits," Thin Solid Films, vol. 53 (1978) pp. 117-128.
R. S. Nowicki et al, "Studies of the TiW/Au Metallization on Aluminum," Thin Solid Films, vol. 53 (1978) pp. 195-205.
Chung Henry W.
Yao Tsui Y.
Haken J.
Hearn Brian E.
Holtzman Laura M.
Meetin R.
North American Philips Corporation, Signetics Div.
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