Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-05-30
2002-10-08
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S189090, C365S230060
Reexamination Certificate
active
06462989
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to integrated circuits in which an analog signal is distributed to multiple components and, more particularly, to locally reducing the effects on the analog signal due to voltage changes on a bus providing the reference for the analog signal.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Integrated circuits typically include multiple signals which are distributed on a semiconductor substrate to various types of components, such as logic circuitry, input circuitry, output circuitry, etc. Such signals include analog signals that may be used to bias some of the components and which typically are referenced to a voltage bus (e.g., a ground) provided on the semiconductor substrate. The reference voltage bus may have a variety of different topologies and may be configured as a shared bus on the substrate to which the various components connect. Alternatively, the reference voltage bus may be configured as multiple independent electrical paths from each of the components to pads on the substrate which are connected to an external reference voltage source.
Many integrated circuit components biased by the analog signal may generate output signals which are particularly sensitive to changes in the bias voltage. For example, integrated circuits, such as memory devices (e.g., SRAMs, DRAMs) typically include output drivers to drive output signals onto a data bus. Many such output drivers include open-drain or open-collector drive elements. When a logical HIGH level data signal is provided on the data bus, the output driver element (e.g., a FET, a BJT, etc.) is in a non-conductive state. To provide a logical LOW level signal on the data bus, the driver element is placed in a conductive state such that an output current flows on the data bus.
The amount of current provided by a driver element generally is dependent on the amount of bias voltage applied to that driver element. Thus, variations of the reference voltage on the reference bus can cause corresponding changes in the output current provided by a driver element. Such variations may be due to resistive drops on the voltage reference bus or inductive effects which cause transients on the reference bus when the driver element switches between conductive and non-conductive states. If the bias voltage signal applied locally to a driver element does not move common mode with the variations on the reference bus, the amount of bias voltage (i.e., the difference between the bias voltage signal and the reference bus) may vary locally at the driver element. Decreases in the local bias voltage at a particular driver element may lead to decreases in the amount of current the particular driver element can provide to the data bus. Increases in the local bias voltage at a particular driver element can steal charge away from other driver elements, thus decreasing the amount of current the other driver elements can provide to the data bus. Weak data signals on the data bus that may result due to the decreased amount of current provided by a driver element potentially may lead to data errors.
Changes in the amount of bias voltage applied locally to a component may be reduced by addressing circuit layout and lead lengths to minimize the parasitic inductance of the integrated circuit package which can cause voltage changes on the reference bus. However, the parasitic inductance cannot be eliminated completely. Thus, to further reduce changes in the amount of bias voltage applied locally to a component, the size of the reference bus may be increased (i.e., the resistance decreased) such that voltage changes on the reference bus are not large enough to impact the output current provided by a driver element. Alternatively, gridding of the reference bus on the substrate may be increased to further reduce voltage changes. Such solutions may not be particularly attractive, however, as they can lead to significant increases in the amount of bussing, thus increasing the size of the integrated circuit. For applications in which minimization of circuit size is desirable, increasing the size of the bus or the amount of bus gridding may not be attractive alternatives.
The present invention may address one or more of the problems set forth above.
REFERENCES:
patent: 4563660 (1986-01-01), McNeilly
patent: 5822166 (1998-10-01), Massie
patent: 5844425 (1998-12-01), Nguyen et al.
patent: 5963057 (1999-10-01), Schmitt et al.
Fletcher Yoder & Van Someren
Ho Tu-Tu
Micro)n Technology, Inc.
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