Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2001-03-30
2002-12-10
Riley, Shawn (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
C323S284000, C323S224000
Reexamination Certificate
active
06492794
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of voltage converters. More particularly, the present invention relates to prevention of over-current conditions in voltage converters.
BACKGROUND OF THE INVENTION
In a conventional voltage converter, an output voltage is typically monitored, compared to a predetermined desired level and a response is developed to more precisely attain the desired output voltage. More particularly, to adjust the output voltage, the input current is modulated up or down. Conventional modulation techniques include pulse-width modulation (PWM) and frequency modulation.
FIG. 1
illustrates a voltage converter of the prior art. An unregulated direct-current DC voltage source Vin
1
is coupled to a first terminal of a switch SW
1
. A second terminal of the switch SW
1
is coupled to a first terminal of an inductor L
1
and to a first terminal of a switch SW
2
. A second terminal of the inductor L
1
is coupled to a first terminal of an output capacitor C
1
. A second terminal of the switch SW
2
and a second terminal of the capacitor C
1
are coupled to ground.
When the switch SW
1
is closed, the switch SW
2
is open. Under these conditions, current flows from the input source Vin
1
through the inductor L
1
and charges the capacitor C
1
. Thus, an output voltage Vout
1
formed across the capacitor C
1
tends to increase. When the switch SW
1
is open, the switch SW
2
is closed. Under these conditions, current from the capacitor C
1
flows through the inductor L
1
and to ground. Thus, the output voltage Vout
1
tends to decrease. A load
10
coupled across the capacitor C
1
is powered by the voltage converter.
A first terminal of a resistor R
1
is coupled to the first terminal of the capacitor C
1
. A second terminal of the resistor R
1
is coupled to a first terminal of a resistor R
2
. A second terminal of the resistor R
2
is second terminal of the capacitor C
1
.
The resistors R
1
and R
2
form a voltage divider, in which a voltage formed at an intermediate node is proportional to the output voltage Vout
1
. This voltage is coupled to an inverting input of an amplifier
12
. A reference voltage Vref
1
is coupled to a non-inverting input of the amplifier
12
. The amplifier
12
forms an error signal Veao
1
that is representative of a difference between the output voltage Vout
1
and a desired level for the output voltage Vout
1
.
The error signal Veao
1
is coupled to a non-inverting input of a comparator
14
. A periodic ramp signal Vramp
1
formed by an oscillator
16
is coupled to an inverting input of the comparator
14
. The comparator
14
forms a switch control signal Vsw
1
that is coupled to the switch SW
1
and to an input of an inverter
18
. An output of the inverter
18
is coupled to the switch SW
2
.
As can be seen from
FIG. 1
, when the error signal Veao
1
is higher than the ramp signal Vramp
1
, the switch control signal Vsw
1
is a logic high voltage. Under these conditions, the switch SW
1
is closed and the switch SW
2
is open. When the error signal Veao
1
is lower than the ramp signal Vramp
1
, the switch control signal Vsw
1
is a logic low voltage. Under these conditions, the switch SW
1
is open and the switch SW
2
is closed.
The ramp signal Vramp
1
rises steadily to a maximum level and then rapidly discharges to a minimum level before the cycle repeats. The error signal Veao
1
generally remains between maximum and minimum levels of the ramp signal Vramp
1
. Thus, for each cycle of the ramp signal Vramp
1
, the switches SW
1
and SW
2
cycle between opened and closed.
When the output voltage Vout
1
decreases, the error signal Veao
1
increases. This increases the duty cycle for the switch SW
1
and, thus, increases the output voltage Vout
1
. When the output voltage Vout
1
increases, the error signal Veao
1
decreases. This decreases the duty cycle for the switch SW
1
and, thus, decreases the output voltage Vout
1
. Accordingly, the output voltage Vout
1
is regulated in a feedback loop.
If the output voltage Vout
1
is significantly below the desired level, then the switch SW
1
may be closed for a significant portion of the time. As a result, the input current can be of a large magnitude. Further, if the input voltage Vin
1
should rise unexpectedly, this can also contribute to a large input current. A large input current may cause damage to elements of the converter, such as the switch SW
1
. Accordingly, it may be desirable to provide a technique for limiting the input current to the converter.
Therefore, what is needed is a technique for limiting the input current to a voltage converter. It is to these ends that the present invention is directed.
SUMMARY OF THE INVENTION
The invention is a current limiting technique for a voltage converter. Parasitic resistance of an inductor in an input path to the converter is used to determine the level of current input to the converter. If the measured current level is excessive, then switching in the converter may be interrupted until the current falls to an acceptable level. Because parasitic resistance is used to detect the input current, rather than a dedicated sensing resistor, fewer components are required. Thus, implementation of the converter and its associated control circuitry is simplified.
In accordance with an aspect of the invention, a modulated input current passes through an inductor of a voltage converter. Associated with the inductor is an inductance value and a parasitic resistance value. An input voltage at a first terminal of the inductor is filtered and compared to an output voltage formed at a second terminal of the inductor. The difference in these values is indicative of a voltage across the parasitic resistor and, thus, is indicative of the input current. When the difference exceeds a predetermined reference level, the input current may be interrupted until the current in the inductor falls to an acceptable level. Current in one or both directions may be monitored for an excessive level. In addition, hysteresis may be employed so as to cause the current in the inductor to fall to a level that is a predetermined amount below the reference level before enabling the input current. Such hysteresis may reduce the frequency in which the input current is interrupted.
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Champion Microelectronic Corp.
Riley Shawn
Westberg Derek J.
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