Technique for incorporating power information in register...

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Power system

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

07146303

ABSTRACT:
A technique for incorporating power information in a register transfer level design involves defining a module representing an integrated circuit block having its own power grid. The integrated circuit block, when in a power off mode effectuated by a deactivation of a clock signal to the integrated circuit, uses a device dependent on a power grid of an adjoining integrated circuit block to preserve output information from the integrated circuit block to the adjoining integrated circuit block.

REFERENCES:
patent: 6467074 (2002-10-01), Katsioulas et al.
patent: 6536028 (2003-03-01), Katsioulas et al.
Dey et al., S. Controller-Based Power Management for Control-Flow Intensive Designs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, No. 10, Oct. 1999, pp. 1496-1508.
Gupta et al., S. Power Modeling for High-Level Power Estimation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, No. 1, Feb. 2000, pp. 18-29.
Koehl et al., J. IBM's 50 Million Gate ASICs, IEEE, Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference, Jan. 2003, pp. 628-634.
Kumar et al., R. Leakage Power Estimation for Deep Submicron Circuits in an ASIC design Environment, Proceedings of the ASP-DAC 2002 7th Asia and South Pacific Design Automation Conference, Proceedings of the 15th International Conference on VLSI Design, Jan. 2002, pp. 45-50.
Papachristou et al., C. A Multiple Clocking Scheme for Low Power RTL Design, Proceedings of the 1995 International Symposium on Low Power Design, ACM Press, Apr. 1995, pp. 1-6.
Eiermann et al., M. Novel Modeling Techniques for RTL Power Estimation, Proceedings of the 2002 International Symposium on Low Power Electronics and Design, ACM Press, Aug. 2002, pp. 323-328.
Ohnishi et al., M. A Method of Redundant Clocking Detection and Power Reduction at RT Level Design, Proceedings of the 1997 International Symposium on Low Power Electronics and Design, Aug. 1997, pp. 131-136.

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