Technique for incorporating a built-in self-test (BIST) of a DRA

Details Technique for incorporating a built-in self-test (BIST) of a DRA Technique for incorporating a built-in self-test (BIST) of a DRA

1996-09-12

1998-05-05

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

057486409

ABSTRACT:
A processing unit having a CPU core, an integrated RAM and a test unit, which may be implemented in either a test unit, which may be implemented in either hardware or software. A built-in self-test of the RAM is designed to run concurrently with the functional vectors used to test the CPU core. Once the core tests have been activated, a control register may be written to by which will activate the built-in self-test. Thus, the BIST and core testing may overlap to minimize test time.

REFERENCES:
patent: 5416783 (1995-05-01), Broseghini et al.
patent: 5450551 (1995-09-01), Amini et al.
Dekker et al., "A Realistic Fault Model and Test Algorithms for Static Random-Access Memories," 1990 IEEE, pp. 1-5.

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