Technique for forming planarized gate structure

Fishing – trapping – and vermin destroying

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437 63, 437186, 437233, 148DIG50, 148DIG86, 148DIG122, 148DIG131, 156640, 156643, 156651, 156644, 357 2311, 357 239, 357 49, 357 59, H01L 2122, H01L 21265

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048187259

ABSTRACT:
A direct moat wafer processing for maximizing the functional continuity of a field oxide layer employs a processing sequence through which respective differently sized apertures are successively formed in the oxide layer. A first of these apertures prescribes the size of the polysilicon gate, while a second aperture is formed around the completed gate structure and prescribes the geometry of source/drain regions to be introduced into exposed surface areas of the substrate on either side of the gate. The sidewalls of the first and subsequently formed, second aperture are effectively perpendicular to the substrate surface, thereby maintaining the functional continuity of the field oxide layer across the entirety thereof. Thereafter, a separate gate interconnect layer is selectively formed atop the field oxide layer to provide a conductive path to the gate.

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patent: 4439270 (1984-03-01), Powell et al.
patent: 4512073 (1985-04-01), Hsa
patent: 4536943 (1984-08-01), Kakuma

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