Semiconductor device manufacturing: process – Chemical etching
Reexamination Certificate
2000-08-23
2002-01-08
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
C438S722000, C438S723000, C438S743000, C438S744000
Reexamination Certificate
active
06337278
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of integrated circuit (“IC”) device structure and processing. More particularly, the present invention relates to a borderless transistor gate and source/drain region contact structure and processing technique of especial utility in providing an on-chip area efficient connection between the device gate layer and an associated source/drain region that can also overlap adjoining isolation structures. In a representative embodiment disclosed herein, such may be effectuated through the overlapping of one portion of the contact region over the edge of the gate polysilicon layer and another part of the contact over the source/drain diffusion.
A number of processing techniques have been described for the formation of contacts between the polysilicon interconnect layer of metal oxide semiconductor (“MOS”) transistor gates and an associated source/drain diffusion. Representative of these are U.S. Pat. No. 4,966,870 to Barber et al. for “Method for Making Borderless Contacts”; U.S. Pat. No. 5,043,790 to Butler for “Sealed Self Aligned Contacts Using Two Nitrides Process”; U.S. Pat. No. 5,104,822 to Butler for “Method for Creating Self-Aligned, Non-Patterned Contact Areas and Stacked Capacitors Using the Method”; U.S. Pat. No. 5,216,281 to Butler for “Self Sealed Aligned Contact Incorporating a Dopant Source”; U.S. Pat. No. 5,385,634 to Butler et al. for “Sealed Self Aligned Contact Process”; U.S. Pat. No. 5,652,176 to Maniar et al. for “Method for Providing Trench Isolation and Borderless Contact”; U.S. Pat. No. 5,674,781 to Huang et al. for “Landing Pad Technology Doubled Up as a Local Interconnect and Borderless Contact for Deep Sub-Half Micrometer IC Application”; and U.S. Pat. No. 5,928,967 to Radens et al. for “Selective Oxide-to-Nitride Etch Process Using C
4
F
8
/CO/AR”. None of the techniques described in the aforementioned patents allow for the formation of a dual contact from a gate polysilicon layer to an associated diffusion that could also overlap adjoining isolation structures.
SUMMARY OF THE INVENTION
Disclosed herein is a borderless transistor gate and source/drain region contact structure and processing technique which provides an on-chip area efficient layout and connection between the device gate layer and an associated source/drain region that can also overlap adjoining isolation structures. In a representative embodiment disclosed herein, this is effectuated through the overlapping of one portion of the contact region over the edge of the gate polysilicon layer and another part of the contact over the source/drain diffusion.
Advantageously, the structure and process of the present invention provides a desirable size reduction in the contact for a given design rule dimension. The contact provided hereby is inherently “self-aligned” to both the gate polysilicon layer and the isolation region in that the contact has no need for an interstitial space between it and the gate polysilicon or isolation regions to prevent unintended electrical connections thereto. In the latter instance, the unwanted connection would be to the semiconductor bulk, or substrate.
Particularly disclosed herein is a method for forming an electrical contact to at least one switching device forming a portion of an integrated circuit device wherein the switching device comprises a pair of substantially coplanar, spaced apart source and drain regions formed in a substrate having a gate terminal insulatedly disposed between the source and drain regions overlying the substrate. The method comprises the steps of: forming an insulating layer overlying the gate terminal proximate to the source and drain regions; forming an antireflective layer overlying the insulating layer and the source and drain regions, with the antireflective layer having a first thickness overlying the insulating layer and a second greater thickness overlying the source, drain and isolation regions. The antireflective layer overlying the insulating layer which overlies the gate terminal is removed to a first thickness thereof and at least a portion of said second thickness of the antireflective layer overlying one of the source or drain regions is also removed by an amount substantially equivalent to the first thickness to provide a remaining third intermediate thickness thereof. The insulating layer overlying the gate terminal is selectively removed to expose an upper surface thereof without substantially removing the third intermediate thickness of the antireflective coating. The process further includes the steps of: removing the third thickness of the antireflective coating layer to expose an upper surface of one of the source or drain regions; forming at least one additional layer at least overlying remaining portions of the insulating layer overlying the gate terminal, the upper surface of the gate layer and the upper surface of one of the source or drain regions; removing a portion of the additional layer to provide an aperture formed therein at least overlying the upper surfaces of the gate terminal and one of the source or drain regions and forming the electrical contact to the gate terminal and the source of drain region within the aperture.
Also disclosed herein is a method for forming an electrical contact to at least one switching device forming a portion of an integrated circuit device wherein the switching device includes a pair of substantially coplanar spaced apart source and drain regions formed in a substrate has a gate terminal insulatedly disposed between the source and drain regions overlying the substrate. The gate terminal and an adjacent conductive region disposed laterally of one of the source and drain regions are covered by respective first and second isolation structures. The method includes the steps of: forming a photoresist layer overlying an upper surface of the integrated circuit device; forming an opening in the photoresist layer overlying at least a portion of the gate terminal and one of the source and drain regions; removing a portion of the first isolation structure overlying at least a portion of an upper surface of the gate terminal within the opening and exposing an upper surface of one of the source and drain regions; removing the photoresist layer; forming at least one additional layer overlying the upper surface of the integrated circuit device including the portion of the upper surface of the gate terminal and the upper surface of one of the source and drain regions; forming an aperture in the additional layer to expose at least the portion of the upper surface of the gate terminal, the upper surface of one of the source and drain regions and at least a portion of an upper surface of the second isolation structure; and forming the electrical contact to the gate terminal and one of the source and drain regions within the aperture.
REFERENCES:
patent: 4966870 (1990-10-01), Barber et al.
patent: 5043790 (1991-08-01), Butler
patent: 5104822 (1992-04-01), Butler
patent: 5216281 (1993-06-01), Butler
patent: 5385634 (1995-01-01), Butler et al.
patent: 5652176 (1997-07-01), Maniar et al.
patent: 5674781 (1997-10-01), Huang et al.
patent: 5928967 (1999-07-01), Radens et al.
Hogan & Hartson LLP
Kubida William J.
Kunemund Robert
Mosel Vitelic Inc.
Umez-Eronini Lynette T.
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