Semiconductor device manufacturing: process – Chemical etching
Reexamination Certificate
2001-08-29
2003-09-02
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
C438S655000, C438S721000, C438S755000
Reexamination Certificate
active
06613673
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or the silicon substrate during gate stack formation. More particularly, the present invention relates to reducing temperature during the fabrication of the gate stack to eliminate the formation of silicon clusters within the metallic silicide film of the gate stack. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.
2. State of the Art
The operating speed of semiconductor devices in very large scale integration (“VSLI”) and ultra large scale integration (“USLI”) depends primarily on the resistivity of the conductive material (hereinafter “trace material”) used to transmit signals from one circuit component to another circuit component. Additionally, in order to increase the circuit component density and/or reduce the complexity of the metal connections between the circuit components, a highly conductive trace material layer is required on the gate stack. Thus, the trace material must be a low-resistivity material.
Metallic silicides have recently become popular for use as low-resistivity trace material. Tungsten silicide (“WSi
x
”) has become a leading low-resistivity trace material. Various etching chemistries have been developed to pattern the WSi
x
to form such conductors as the digitlines or wordlines used in memory devices (see commonly-owned U.S. Pat. No. 5,492,597, hereby incorporated herein by reference). Other metallic silicides used in gate stacks include cobalt silicide (“CoSi
x
”), molybdenum silicide (“MoSi
x
”), and titanium silicide (“TiSi
x
”). These metallic silicides have lower resistivity and are easier to fabricate than other conductors used for this purpose. However, metallic silicides are prone to oxidization. Furthermore, the metal components of the metallic silicides react chemically when they contact other elements. These properties present several problems, including degradation of the semiconductor element and peeling of the metallic silicide film. To compensate for these problems, a polysilicon layer is usually disposed between a gate dielectric layer and the metallic silicide film, and a dielectric cap layer is usually disposed above the metallic silicide film to isolate the metallic silicide.
FIGS. 14-19
illustrate, in cross section, a conventional method of forming a gate stack having a metallic silicide film layer.
FIG. 14
illustrates a gate dielectric layer
204
such as silicon dioxide (SiO
2
) grown (by oxidation) or deposited (by any known industry standard technique, such chemical vapor deposition or the like) on a silicon substrate
202
. A polysilicon layer
206
is formed on top of the gate dielectric layer
204
, as shown in FIG.
15
. The polysilicon layer
206
is then subjected to an ion implantation with gate impurities (not shown). As shown in
FIG. 16
, a metallic silicide film
208
is deposited on the polysilicon layer
206
. The structure is then subjected to a heat treatment for about 30 minutes at a temperature between about 850° C. and 950° C. for activation of the impurities in the polysilicon layer
206
and to anneal the metallic silicide film
208
. The heat treatment temperature level is dictated by the temperature required to anneal the metallic silicide film
208
. The annealing of the metallic silicide film
208
is used to reduce its resistivity.
As shown in
FIG. 17
, a silicon dioxide cap
210
is then deposited on the metallic silicide film
208
at temperatures over 600° C. by chemical vapor deposition (“CVD”), low pressure chemical vapor deposition (“LPCVD”), or the like. A resist
212
is then formed and patterned on the silicon dioxide cap
210
, as illustrated in FIG.
18
. The layered structure is then etched and the resist
212
is stripped to form a gate stack
214
, as illustrated in FIG.
19
. However, this etching results in pitting on the gate dielectric layer
204
. This pitting is illustrated in
FIG. 20
wherein a plurality of pits
216
is distributed on the gate dielectric layer
204
between the gate stacks
214
.
This pitting is also illustrated in
FIG. 19. A
pit in the dielectric layer
204
may be shallow, such as shallow pit
218
. However, a deep pit, such as deep pit
220
, can extend through the gate dielectric layer
204
and into the silicon substrate
202
. The pitting into the silicon substrate
202
will cause junction leakage, refresh problems, and potential destruction of the component. At present, most gate dielectric layers are about 80 Å thick. However, as semiconductor devices continue to be miniaturized, these gate dielectric layers will become thinner. As the gate dielectric layers become thinner, it is more likely that pitting will penetrate through the gate dielectric layer to contact the silicon substrate and cause the aforementioned problems.
Therefore, it would be advantageous to develop a technique which minimizes or eliminates pitting on the gate dielectric layer caused by gate stack etching, while using state-of-the-art semiconductor device fabrication techniques employing known equipment, process steps, and materials.
BRIEF SUMMARY OF THE INVENTION
The present invention relates to the reduction of the temperature during the fabrication of the gate stack to eliminate the formation of silicon clusters within a metallic silicide film of the gate stack. The elimination of the formation of the silicon clusters minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation. The present invention also includes methods for implanting the gate stack layers to disperse the silicon clusters (if they are present in the metallic silicide film) prior to the gate etch step.
One aspect of the method of the present invention begins by forming a gate dielectric layer on a silicon substrate. A polysilicon or amorphous silicon layer (hereinafter “polysilicon layer”) is then formed on top of the gate dielectric layer. The polysilicon layer is subjected to an ion implantation with gate impurities and a non-annealed metallic silicide film is thereafter deposited atop the polysilicon layer. A dielectric cap layer is then deposited over the metallic silicide film at a sufficiently low temperature such that the metallic silicide does not anneal. A resist mask is placed over the cap layer and the structure is etched down to the gate dielectric layer to form a gate stack.
Metallic silicides are generally represented by the formula “MSi
x
” wherein: “M” is the metal component (i.e., cobalt “Co,” molybdenum “Mo,” titanium “Ti,” tungsten “W,” and the like), “Si” is silicon, and “x” is the number of silicon molecules per metal component molecule (“x” is usually between about 2 and 3). Metallic silicide films tend to peel when a low ratio of silicon to metal component is used for gate stack formation (e.g., when “x” is less than 2). In order to reduce the stress of metallic silicide film which causes peeling, a silicon rich metallic silicide film is used in gate stack formation. In particular with the use of WSi
x
, an “x” of about 2.3 is preferred.
In prior art techniques, the metallic silicide is annealed to form a crystalline structured metallic silicide film
502
, as illustrated in
FIG. 23
, between a polysilicon layer
504
(atop a gate dielectric layer
506
, which is on a silicon substrate
508
) and a silicon dioxide layer
510
(below a dielectric cap
512
). However, when a silicon rich metallic silicide is used, the annealing step causes the silicon within the metallic silicide to form clusters
514
inside the crystalline structured metallic silicide film
502
. These silicon clusters
514
can also form during the subsequent high temperature steps, even if the annealing step does not take place. In specific process terms, the step of forming a dielectric cap over the metallic silicide can exceed 600° C., particularly when deposition techniques such as LPCVD and sputtering are u
Iyer Ravi
Liu Louie
Pan Pai-Hung
Powell William A.
TraskBritt
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