Technique for digitally detecting bit-error densities that occur

Details Technique for digitally detecting bit-error densities that occur Technique for digitally detecting bit-error densities that occur

1992-06-25

1994-04-19

Canney, Vincent P.

Excavating

371 55, G06F 1130

Patent

active

053053230

ABSTRACT:
Apparatus, and an accompanying method, for accurately detecting bit-error densities in a serial bit stream and particularly relatively low bit-error densities. Specifically, detected bit-errors are synchronized to a bit clock using a error retiming circuit (130). Subsequently, the bit-errors are counted using a first counter (165) during a pre-defined measurement interval, equivalent to a specified number of bit clock cycles. A second counter (205) establishes the measurement interval by counting the specified number of bit clock pulses. Whenever the first counter attains a count larger than a pre-defined count, during the measurement interval, an output (alarm) signal is generated to indicate that a pre-defined threshold error density has been exceeded. Both the first and second counters are then reset at the conclusion of the measurement interval, and so on for successive measurement intervals. To assure that the measured bit-error density declines to a sufficiently low value before the output signal terminates, the measurement interval is extended once the output signal occurs. Hence, output signal is produced when the pre-defined threshold is exceeded but is reset only when the actual measured bit-error density decreases, typically by an order of magnitude, below the threshold error density.

REFERENCES:
patent: 5138616 (1992-08-01), Wagner, Jr. et al.
patent: 5166890 (1992-11-01), Smischny

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