Technique for designing a bias circuit for an amplifier in an in

Details Technique for designing a bias circuit for an amplifier in an in Technique for designing a bias circuit for an amplifier in an in

1998-07-20

2000-05-30

Lee, Benny

Amplifiers

With semiconductor amplifying device

Including differential amplifier

330261, H03F 345

Patent

active

060695323

ABSTRACT:
In a class AB amplifier circuit for use in an integrated circuit (IC) device, a bias circuit is used to bias a first field effect transistor (FET) in an output stage. A second FET in the bias circuit is connected to the first FET. The drain current of the first FET contributes to the output of the amplifier circuit. In response to a difference in inputs to the amplifier circuit in a transient state, the second FET operates in a non-saturation mode especially when the voltage of the power supply to the amplifier circuit is required to be low, e.g., 2 volts. As a result, an input voltage to the first FET which operates in a saturation mode increases, thereby increasing its drain current contributing to the amplifier circuit output. This increased drain current advantageously prevents the otherwise significant distortion in the amplifier circuit output during the transient state.

REFERENCES:
patent: 4893092 (1990-01-01), Okamoto et al.
patent: 5442319 (1995-08-01), Seesink et al.
patent: 5907259 (1999-05-01), Yamada et al.

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