Technique for creating different mechanical strain in...

Details Technique for creating different mechanical strain in... Technique for creating different mechanical strain in...

2006-06-07

2009-10-27

Rose, Kiesha L. (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

C257SE27108, C257S371000, C257S369000, C257S288000

Reexamination Certificate

active

07608912

ABSTRACT:
The present invention provides a technique for reducing stress or stress gradients in highly sensitive device regions, such as cache areas, while still providing high transistor performance in logic areas by correspondingly providing contact etch stop layers with compressive and tensile stress for P-channel transistors and N-channel transistors in these logic areas. Consequently, a reduced failure rate may be obtained.

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patent: 2004/0029323 (2004-02-01), Shimizu et al.
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patent: 2006/0099763 (2006-05-01), Liu et al.
patent: 2006/0189075 (2006-08-01), Kanno
patent: 2006/0226490 (2006-10-01), Burnett et al.
patent: 2007/0042579 (2007-02-01), Runyon et al.

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