Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Reexamination Certificate
2000-08-25
2002-10-29
Potter, Roy (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
C257S700000, C257S786000
Reexamination Certificate
active
06472725
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an improved method for the electrical attachment of a semiconductor die to the leads of a lead frame and the apparatus formed therefrom. More particularly, the present invention relates to the use of multi-layered or laterally-segmented metal/elastomer strips to achieve electrical contact between the bond pads of a semiconductor die and the leads of a lead frame or other conductor pattern in order to eliminate the necessity for wirebonding or direct lead bonding (TAB) to the semiconductor die.
2. Background Art
The most common die-connection technology in the microelectronics industry is wirebonding. As illustrated in
FIG. 6
, wirebonding generally starts with a semiconductor die
30
bonded by a die-attach adhesive such as a solder or an epoxy to a lead frame paddle or to a discrete substrate
29
. A plurality of bond wires
32
are then placed, one at a time, to electrically connect the bond pads
34
to their corresponding leads
36
. One end of each bond wire is attached to a bond pad
34
of the semiconductor die
30
, and the other bond wire end is attached to a lead
36
.
The bond wires
32
are attached through one of three industry standard wirebonding techniques: ultrasonic bonding—using a combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld, resulting in a so-called wedge-wedge wire bond; thermocompression bonding—using a combination of pressure and elevated temperature to form a weld, resulting in a so-called ball-wedge wire bond; and thermosonic bonding—using a combination of pressure, elevated temperature, and ultrasonic vibration bursts, resulting in a ball-wedge bond similar to that achieved by thermocompression bonding. Although these wirebonding techniques accomplish the goal of forming electrical contact between the semiconductor die
30
(i.e. through the bond pads
34
) and each lead
36
, all of these techniques have the drawback of requiring very expensive, high-precision, high-speed machinery to attach the individual bond wires
32
between the individual bond pads
34
and the leads
36
. Moreover, the preferred bond wire material is gold, which becomes extremely expensive for the vast quantities employed in commercial semiconductor fabrication. Other materials employed in the art, such as silver, aluminum/silicon, aluminum/magnesium, and palladium, while less expensive than gold, still contribute significantly to the cost of achieving die/lead frame electrical connections.
U.S. Pat. No. 4,862,245 issued Aug. 29, 1989 to Pashby et al. illustrates an alternate lead arrangement on the semiconductor die (see FIG.
7
). The leads
46
are extended over a semiconductor die
40
(“leads over chip” or LOC) toward a central or axial line of bond pads
44
wherein bond wires
42
make the electrical connection between the inner ends of leads
46
and the bond pads
44
. Film-type alpha barriers
48
are provided between the semiconductor die
40
and the leads
46
, and are adhered to both, thus eliminating the need for a separate die paddle or other die support aside from the leads
46
themselves. The configuration of the '245 patent assists in limiting the ingress of corrosive environmental contaminants to the active surface of the die, achieves a larger portion of the circuit path length encapsulated in the packaging material applied after wire bonding, and reduces electrical resistance caused by the bond wires
42
by placing the lead ends in closer proximity to the bond pads (i.e., the longer the bond wire, the higher the resistance). Although this configuration offers certain advantages, it still requires that bond wires
42
be individually attached between the bond pads
44
and the leads
46
.
U.S. Pat. No. 5,252,853 issued Oct. 12, 1993 to Michii illustrates a configuration similar to U.S. Pat. No. 4,862,245 discussed above. However, the lead is further extended to a position over the bond pad wherein the lead is bonded directly to the bond pad (TAB). Although this direct bonding of the lead to the bond pad eliminates the need for wirebonding, it still requires expensive, highly precise equipment to secure the bond between each lead and its corresponding bond pad.
U.S. Pat. No. 5,140,405 issued Aug. 18, 1992 to King et al. addresses the problem of connecting dies to leads by placing a plurality of semiconductor dies in a housing which is clamped to a plate having conductive pads and leads which are precisely aligned with the terminals of the semiconductor dies. A sheet of anisotropically conductive elastomeric material is interposed between the housing and the plate to make electrical contact. The anisotropically conductive elastomeric material is electrically conductive in a direction across its thickness, but non-conductive across its length and width, such as material generally known as an “elastomeric single axis conductive interconnect”, or ECPI.
Although the technique of achieving electrical contact between the semiconductor dies and the leads in U.S. Pat. No. 5,140,405 is effective for a plurality of chips, the scheme as taught by the '405 patent is ill-suited for the production of single chips in commercial quantities. The requirement for a housing and the use of a conductive sheet which covers both the housing surface and the semiconductor dies is simply not cost effective when translated to mass production, single-chip conductor attachment or conductor attachment on less than a substantially wafer scale.
A further industry problem relates to burn-in testing of semiconductor dies. Burn-in is a reliability test of semiconductor dies to identify dies which are demonstrably defective as fabricated, or which would fail prematurely after a short period of proper function. Thus, the die is subjected to an initial heavy duty cycle which elicits latent silicon defects. The typical burn-in process consists of biasing the device against a circuit board or burn-in die, wherein the device is subject to an elevated voltage load while in an oven at temperatures of between about 125-150° C. for approximately 24-48 hours.
A burn-in die generally comprises a sheet of polyimide film laminated to copper foil leads with electrolytically plated metal bumps which extend from the surface of the polyimide film through vias to the copper foil leads. However, the industry standard process for electrolytically plating bumps generally results in different circuit intensities to each copper foil lead on the burn-in die due to the use of individual tie bars as electrical paths between a bus bar and the bump ends of the leads disposed in the plating bath. The differences in circuit intensities caused by the variable cross-sections of the tie bars extending to each copper foil lead result in the plated bumps being non-uniform in diameter and height. The differences in bump diameter and height consequently make uniform contact with the terminals on the semiconductor dies to be tested much more difficult. In general, the connection between the semiconductor die and the burn-in die is non-permanent, wherein the semiconductor die is biased with a spring or the like in the burn-in die such that the bond pads on the semiconductor die contact the plated bumps. Thus, even minor variations between the plated bump heights may result in one or more die terminals failing to make contact with one or more plated bumps. This lack of contact will result in a portion of the semiconductor device not being under a voltage load during the burn-in process. Thus, if a latent silicon defect exists in this portion of the semiconductor device, the burn-in process will not be effective and the die cannot be effectively electrically tested in the region where the open circuit exists.
U.S. Pat. No. 5,408,190 issued Apr. 18, 1995 to Wood et al. discloses the use of a Z-axis anisotropic conductive sheet of material to electrically connect the bond pads of a die to an intermediate substrate employed in a burn-in assembly for a bare die. However, it appears that a sheet
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