Technique and circuit for providing two or more processors with

Details Technique and circuit for providing two or more processors with Technique and circuit for providing two or more processors with

1992-11-25

1995-11-28

Harvey, Jack B.

Boots, shoes, and leggings

364DIG1, 3642315, 364238, 3642385, 3642386, 364230, 3642436, 395729, G06F 1300

Patent

active

054715881

ABSTRACT:
A time multiplexing technique and corresponding circuitry which provides controlled access to one processor at a time of two or more access requesting processors, to a system resource shared by the two or more processors. Each of the access requesting processors is connected to an input of a plurality of multiplexers. Each of the multiplexers has a select input which determines which of the multiplexer's inputs becomes its output which is in turn, connected to an appropriate input of the system resource. By connecting together the select inputs of the multiplexers, access to the shared system resource is alternated between the two or more processors by alternating the value of the select input in response to the system clock.

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