Technique and apparatus for testing an electrically programmable

Details Technique and apparatus for testing an electrically programmable Technique and apparatus for testing an electrically programmable

1993-03-26

1994-12-06

Cosimano, Edward R.

Excavating

364579, 364580, 371 211, 371 212, 371 226, G06F 1100, G06F 1122, G11C 2900

Patent

active

053717481

ABSTRACT:
A method and apparatus for testing an electrically programmable read-only-memory which is embedded within logic or other digital circuitry on an integrated circuit is described. An integrated circuit tester is used to test the electrically programmable read-only-memory along with the logic or other digital circuitry by encoding certain test channels of the integrated circuit tester, and inputting the encoded test channels into a high voltage signal decoding circuit specially adapted to generating a high voltage, programming voltage required by the electrically programmable read-only-memory when the programming of certain test bits in the electrically programmable read-only-memory is conducted.

REFERENCES:
patent: T930005 (1975-01-01), Chia et al.
patent: 3082374 (1963-03-01), Buuck
patent: 3237100 (1966-02-01), Chalfin et al.
patent: 3492872 (1970-01-01), Jones et al.
patent: 3714403 (1973-01-01), Ammann et al.
patent: 3961252 (1976-06-01), Eichelberger
patent: 4519078 (1985-05-01), Komonytsky
patent: 4559626 (1985-12-01), Brown

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