Multiplex communications – Channel assignment techniques – Combining or distributing information via time channels...
Reexamination Certificate
1998-06-11
2003-02-18
Hsu, Alpus H. (Department: 2665)
Multiplex communications
Channel assignment techniques
Combining or distributing information via time channels...
C370S503000, C370S509000
Reexamination Certificate
active
06522659
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a time division multiple access (TDMA) voice information reading apparatus for reading out voice data from data received by TDMA and, more particularly, to a TDMA voice information reading apparatus which delays voice data until synchronous detection even upon receipt of out of frame reception data (e.g., a pull-out of reception data) in a transmission line such as a radio channel, thereby normally reading out the voice data and outputting it.
2. Description of the Prior Art
Conventionally, a TDMA voice information reading apparatus of this type is applied to, e.g., a portable telephone. In this case, the timing of reception data sometimes shifts from the original timing due to the distance from a cell base station connected via a radio channel or multiple radio wave propagation (multipath) at an obstacle at the moving position. That is, voice data out of phase may be received.
A “bit synchronization circuit” disclosed in Japanese Unexamined Patent Publication No. 4-10725 is known as a measure against such reception data out of phase. In this prior art, when a pull-out occurs, erroneous data is not read out from the FIFO memory. That is, the data out of phase is discarded.
FIG. 1
is a block diagram showing the arrangement of main part (TCH (Traffic Channel) read circuit) of a conventional TDMA voice information reading apparatus. Referring to
FIG. 1
, the TCH read circuit has a TCH data read window generation circuit
13
for generating TCH data read window data S
1
of high level at a free-running timing. The TCH read circuit also has an AND gate
12
for receiving the TCH data read window data Si and reception data S
2
and outputting voice output data S
14
to a digital signal processor (DSP) (not shown) for processing speech communication voice data, and a synchronous detection circuit
5
for detecting synchronization from the reception data S
2
and sending bit shift data S
8
representing the shift of the reception data S
2
from the prescribed timing to the TCH data read window generation circuit
13
.
FIGS. 2A
to
2
C are process timing charts showing the operation of the conventional TDMA voice information reading apparatus. In
FIGS. 1 and 2A
to
2
C, the standards of a digital mobile telephone system to which the TCH read circuit in the TDMA voice information reading apparatus is applied are defined on the basis of “RCR-27D”. In this system, a synchronization code word for synchronous detection is set in a reception slot, as shown in FIG.
2
A.
The TCH data read window data S
1
of high level is generated by the TCH data read window generation circuit
13
at a free-running timing as shown in FIG.
2
B and input to one input terminal of the AND gate
12
. The reception data S
2
is input to the other input terminal of the AND gate
12
and the synchronous detection circuit
5
. The synchronous detection circuit
5
detects the bit shift data S
8
representing the shift of the reception data
52
from the prescribed timing and outputs the bit shift data S
8
to the TCH data read window generation circuit
13
.
When the synchronous detection circuit
5
detects the bit shift, an erroneous data portion in the reception data has already been output from the AND gate
12
to the DSP as TCH data or the voice output data S
14
. In this case, the DSP cannot perform normal voice data processing. As a result, the TCH data of the current slot cannot be processed as normal voice data although the synchronous timing of the next slot can be calculated from the bit shift data obtained from the current slot. Therefore, the channel quality degrades.
As described above, in the conventional TDMA voice information reading apparatus, TCH data of the current slot cannot be processed as normal voice data although the synchronous timing of the next slot can be calculated from the bit shift data obtained from the current slot. Therefore, the channel quality degrades to result in a low transmission efficiency and low reliability of data transmission.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the above situation of the prior art, and has as its object to provide a TDMA voice information reading apparatus which can normally output TCH data of a current slot as voice data even when data based on time division multiple access is received with a pull-out due to degradation in channel quality, thereby largely improving the transmission efficiency and reliability of transmission.
A TDMA voice information reading apparatus of the present invention comprises processing means for, in a pull-out of reception data based on time division multiple access, delaying the reception data pulling out synchronization and detecting synchronization before the reception data is read out, and then reading out voice data and outputting the voice data in order to normally read out and output the voice data.
In the TDMA voice information reading apparatus of the present invention, a delay time until the reception data is read out is a minimum time for synchronous detection.
In the present invention, phase matching of a read signal associated with a timing at which the voice data in the reception data is read out is adjusted by delaying the read signal or reception data in units of bits.
In order to achieve the above object, according to the first aspect of the present invention, there is provided a TDMA voice information reading apparatus comprising:
(a) a first shift register for storing, in units of bits, window data used to read out the voice data in the reception data, reading out the window data, and outputting the window data;
(b) a second shift register for storing reception data of a slot in units of bits and outputting the reception data with a timing shift of several bits before or after a synchronization code word stored in a reception slot on the basis of the reception data received at a prescribed timing;
(c) a synchronous detection circuit for comparing, in units of slots, a reception timing of the synchronization code word in the reception data with a free-running pulse internally generated at a prescribed timing and outputting bit shift data representing a phase shift of the timing;
(d) an AND gate for sending voice output data obtained by ANDing read window data phase-matching the voice data in the reception data and reception data delayed until establishment of synchronization, which is output from the second shift register;
(e) a selector for selecting the read window data and outputting the read window data phase-matching the voice data in the reception data on the basis of the bit shift data representing the position and the number of bits shifted from the prescribed timing, which is output from the synchronous detection circuit after reception of the synchronization code word in the slot; and
(f) a voice data read window generation circuit for generating the read window data at a free-running timing allowing reception of a synchronization code word in the next slot after reception of the synchronization code word in the preceding slot.
In order to achieve the above object, according to the second aspect of the present invention, there is provided a TDMA voice information reading apparatus comprising:
(a) a voice data read window generation circuit for generating read window data at a free-running timing allowing reception of a synchronization code word in the next slot after reception of a synchronization code word in a preceding slot;
(b) a first shift register for delaying the read window data from the voice data read window generation circuit in units of bits and outputting the read window data;
(c) a second shift register for storing reception data in units of bits and outputting delayed reception data;
(d) a synchronous detection circuit for comparing, in units of slots, a reception timing of the synchronization code word in the reception data with a free-running pulse internally generated at a prescribed timing and outputting bit shift data representing a phase
Hsu Alpus H.
McGinn & Gibb PLLC
NEC Corporation
Stevens Roberta
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