Electrical computers and digital processing systems: multicomput – Network-to-computer interfacing
Reexamination Certificate
2008-05-20
2008-05-20
Etienne, Ario (Department: 2157)
Electrical computers and digital processing systems: multicomput
Network-to-computer interfacing
C709S250000, C709S212000, C370S386000, C711S005000
Reexamination Certificate
active
10459349
ABSTRACT:
A TCP/IP processor and data processing engines for use in the TCP/IP processor is disclosed. The TCP/IP processor can transport data payloads of Internet Protocol (IP) data packets using an architecture that provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol layer and may also provide packet inspection through Layer 7. The engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a TCP/IP session information database and may also store a storage information session database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory. An application running on an initiator or target can in certain instantiations register a region of memory, which is made available to its peer(s) for access directly without substantial host intervention through RDMA data transfer.
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Armstrong Teasdale LLP
Etienne Ario
Halim Sahera
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