Task and stack manager for digital video decoding

Details Task and stack manager for digital video decoding Task and stack manager for digital video decoding

1997-05-30

1999-07-27

Eng, David Y.

Electrical computers and digital processing systems: multicomput

Computer-to-computer data routing

Least weight routing

G06F 1300

Patent

active

059283211

ABSTRACT:
A reduced instruction set CPU is programmed to provide software-controlled task management, a stack, and to manage virtual instruction memory. The CPU performs a task management procedure in which the CPU repeatedly checks task flags, and if a task flag is set, performs the task associated with the set task flag. If multiple task flags are set, the highest priority task of those associated with set task flags is performed. Whenever a subroutine call is needed, the subroutine call is implemented by calling a stack management routine. The stack management routine retrieves and stores a return address into a location in DRAM identified by a stack pointer, increments the stack pointer, and then executes a CALL instruction, causing program execution to sequence to the desired subroutine. At the end of each subroutine, a RETURN instruction is executed, in response to which, program execution returns to the stack management routine, and the stack management routine decrements the stack pointer, loads the previously-stored return address from a location in DRAM identified by the stack pointer register, and then causes program execution to sequence to the loaded return address. The stack management routine also provides virtual instruction memory management, by determining whether a routine is resident in the on-chip instruction memory available to the RISC CPU prior to calling or returning to the routine. If not, the virtual instruction memory management routine transfers the desired routine from off-chip DRAM into the on-chip instruction memory, and then executes the call or return.

REFERENCES:
patent: 5499370 (1996-03-01), Hosaka et al.
patent: 5528513 (1996-06-01), Vaitzblit et al.
IBM Corp., Masking Peripheral Interrupts, IBM Technical Disclosure Bulletin, vol. 24, No. 11A, Apr. 1982, pp. 5362-5363.
IBM Corp., IOP Task Switching, IBM Technical Disclosure Bulletin, vol. 33, no. 5, Oct. 1990, pp. 156-158.
Anzinger, George A., Managing PA-RISC Machines for Real-Time Systems, 1266 Hewlett-Packard Journal, 44(1993) Aug., No. 4, pp. 31-37.
Hills, Ted, Structured Interrupts, 8283 Operating Systems Review (SIGOPS) 27 (1993) Jan., No. 1, pp. 51-68.
IBM Corp., Asynchronous Task Scheduler, IBM Technical Disclosure Bulletin, vol. 14, No. 10, Mar. 1972, pp. 3192-3193.

Affiliated with

Also associated with

Rating

Task and stack manager for digital video decoding does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Task and stack manager for digital video decoding, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Task and stack manager for digital video decoding will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-873733