Target configuration and method for extraction of overlay vector

Details Target configuration and method for extraction of overlay vector Target configuration and method for extraction of overlay vector

1999-02-02

2000-11-14

Bowers, Charles

Semiconductor device manufacturing: process

With measuring or testing

438401, G01R 3126, H01L 2166

Patent

active

061469106

ABSTRACT:
A method is provided for extracting overlay information from a target of an integrated circuit wafer wherein the first-level target has features wh are optically concealed by an overlying opaque planarized film. The target employed has an architecture including a resist feature on the planarized film and an embedded electron backscattering target feature disposed beneath the planarized film. This target is scanned with an electron bean of an energy sufficiently high (e.g., at least 11 keV) to penetrate the planarized film, be backscattered by the backscattered feature and return through the planarized film or through the planarized film and the resist feature. Electrons backscattered from the conductive first-level target feature through the resist feature are detected and a signal profile is generated based thereon. This signal profile is analyzed to extract overlay information.

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