Tapered via, structures made therewith, and methods of producing

Details Tapered via, structures made therewith, and methods of producing Tapered via, structures made therewith, and methods of producing

1996-11-08

2000-04-04

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438397, 438253, 438254, H01L 2120

Patent

active

RE0366447

ABSTRACT:
After formation of the storage poly in a stacked capacitor DRAM, the oxide 1 layer is partially etched to leave a thick oxide deposition in the area of the future bit line contact, upon which the cell poly is deposited, followed by oxide 2 and then a poly or nitride layer. A mask and etch process forms the bit line contact region through the cell poly, then a thin oxide is deposited and etched along with the oxide 1 to form cell poly spacers that don't close off the active area. The poly or nitride on top of the oxide 2 forms a hard mask that allows the spacers to travel down the side walls of the contact region creating a contact region that is wider at the top than bottom, facilitating metalization.

REFERENCES:
patent: 4543707 (1985-10-01), Ito et al.
patent: 5061651 (1991-10-01), Ino
patent: 5077238 (1991-12-01), Fuji et al.
patent: 5135881 (1992-08-01), Saelci
patent: 5150276 (1992-09-01), Gonzales
Kawamoto et al., "A 1.28 .mu.m Bit-Line Shielded Memory Cell Technology for 64 Mb DRAM", Symposium on VLSI technology, pp. 13-14, 1990.
Itoh et al., "Two Step Deposited Rugged Surface (TDRS) Storagenode and Self Aligned Bitline-Contact Penetrating Cellplate (SABPEC) for 64 MbDRAM STC Cell" IEEE Symposium on VLSI Technology, pp. 9-10, 1991.
Shibata et al., "A Novel Zero-Overlap/Enclosure Metal Interconnection Technology for High Density Logic VLSI's", IEEE VMIC Conference, pp. 15-21, 1990.

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