Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2000-08-31
2002-07-02
Zarabian, Amir (Department: 2824)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S106000, C438S127000
Reexamination Certificate
active
06413796
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to a tape for semiconductor package used to attach a chip and a lead frame or a chip and a substrate, method of manufacturing the same, and method of manufacturing the package using the tape, and more particularly to, a tape for semiconductor package, method of manufacturing the same, and method of manufacturing the package using the tape, in which a tape for semiconductor package of a sheet type or a roll type is formed in which a thermoplastic pattern matching to the lead frame or the portion to which the chip of the substrate is bonded, is provided, thus, reducing the cost and improving the productivity.
DESCRIPTION OF THE PRIOR ART
Generally, the semiconductor package includes various types of packages, such as the package in which chips are bonded to the lead frames like the package of lead on chip (LOC) type, the package in which chips are bonded to the substrate like a chip scale package (CSP), for example, a micro ball grid array (&mgr;BGA) package, etc. Recently, as electronic devices become miniaturized and thinner, it is required that the package also be miniaturized and thinner. Specially, in order to enhance the competitiveness between the manufacturing companies, it is required that the productivity be improved and the cost be reduced. As one way of improve the productivity and reduce the cost, a method of simplifying the process of manufacturing the package, has been proposed.
FIG. 1
is a sectional view of a conventional lead on chip type for attaching a chip to a lead frame. The lead on chip package
10
includes a chip
11
, a lead frame
12
, an attachment layer
13
for attaching the chip
11
and the lead frame
12
, a wire
14
for electrically connecting the chip
11
and the lead frame
12
, and a protective layer
15
for protecting the chip
11
and the wire
14
from outside various damage.
FIG. 2
is a sectional view of a conventional chip scale package for attaching a chip to a substrate. The chip scale package
20
includes a chip
21
, a substrate
22
, an attachment layer
23
for attaching the chip
21
and the substrate
22
, a lead
24
for electrically connecting the chip
21
and the substrate
22
, a protective layer
25
for protecting the chip
21
and the lead
24
from outside various damage, and a solder ball
26
formed below the substrate
22
.
The basic manufacturing process of the lead on chip type package
10
and the chip scale package
20
sequentially includes a wafer dicing saw process of individually separating the chips
11
,
21
from the wafer, a chip attachment process of attaching the chips
11
,
21
to the lead frame
12
or the substrate
22
, a wire/lead attachment process of electrically connecting the chips
11
,
21
and the lead frame
12
or the substrate
22
, a molding and sealing process of protecting the chips
11
,
21
from various damage factors, thus completing a assembly process.
After the assembly process, the package of lead on chip type
10
is manufactured by sequentially performing a mechanical/chemical deflash process, a tin plating process, a trim process, a form/singulation process, a pretest process, a burn-in test process, a post test process, etc., so that individual devices can be separated from the lead frame strip consisted of lead frame units and their lead shapes can be formed into a prescribed shape, thus functioning as a complete integrated circuit (IC), after the above assembly process.
The chip scale package
20
is pasted with a solder flux, after the above mentioned assembly process, and is manufactured by sequentially performing a solder ball attachment process, a reflow process and a singulation process.
Among the above mentioned package manufacturing process, the attachment layers
13
,
23
used in the chip attachment process for attaching the chip
11
and the lead frame
12
or the chip
21
and the substrate
22
are formed of tape slices
31
made by cutting the tape
30
of a conventional three-layer structure shown in
FIG. 3
into a constant size, using a cutting tool. The three-layer structure
30
is formed of films
32
and
34
made of adhesives at the top and bottom sides of the base film
33
. Meanwhile, the elastomer is an adhesive mainly used in the chip scale package
20
and is formed with a nubbin type, etc. Generally, though a method of using the tape of three-layer structure is widely used in the chip attachment process, as mentioned above, in the chip scale package, a method of attaching the chip by which the tape of a three-layer structure is attached, a coating solution is dropped or a screen-printing is applied to cure it, and adhesive is dropped or a screen-printing is applied to cure it, is also used.
The process of attaching the chip
11
and the lead frame
12
in
FIG. 1
will be now explained by reference to
FIG. 4
using the tape slice
31
.
FIG. 4
is a diagram for explaining the processes of attaching the chip
11
to the lead frame
12
of the lead frame strip
40
using a conventional tape slice
31
. The lead frame strip
40
is consisted of a number of lead frame units
40
A,
40
B and
40
C. The tape slice
31
in
FIG. 3
is attached to the lead frame units
40
A,
40
B and
40
C, respectively. Then, the chip
11
is raised to the tape slice
31
and the chip
11
and the lead frame
12
are attached by means of curing and press.
The process of attaching the chip
21
and the substrate in
FIG. 2
is same to the principle of attaching process explained by reference to FIG.
4
.
As explained above, in the package in which the chip is attached to the lead frame as in the package of lead on chip type and the package in which the chip is attached to the substrate as in the chip scale package, there are various types of methods to attach the chip and the lead frame or the chip and the substrate. When using the three-layer structure tape, there are problems that the cutting tool is necessarily required, the manufacture of the lead frame is difficult regarding to the cutting burr, the productivity is lowered and void is generated between the lead and the lead. In case of dropping a coating solution after the three-layer structure tape is attached or in case of dropping adhesive later after a screen-printing is applied to cure it, there are problems that not only a lot of time can be consumed but also it is difficult to drop adhesive at an exact position. Also, there are problems that it is difficult to control its height in case of using elastomer and it is difficult to remove void in case of a nubbin type. Therefore, the conventional chip attachment process consumes a lot of time, this causing lower of the productivity and thereby lower of throughput of the product due to above problems.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a tape for semiconductor package, method of manufacturing the same and method of manufacturing the package using the tape, which can reduce the cost and improve the productivity, by providing a tape for semiconductor package of a sheet type or a roll type in which a thermoplastic pattern matching to the lead frame or the portion to which the chip of the substrate is attached.
In order to accomplish the above object, the tape for a semiconductor package is characterized in that it comprises a base film to side of which a release film is applied; a plurality of alignment holes formed at the edge of said base film; and a thermoplastic pattern formed on said release film so that it can match to a lead frame or the portion to which a chip of a substrate is attached.
Further, in order to accomplish the above object, the method of manufacturing a tape for a semiconductor package is characterized in that it comprises the steps of providing a base film; applying a release film at one side of said base film; forming, at a given distance, a plurality of alignment holes along the edge of said base film; and forming a thermoplastic pattern on said release film so that it can match to a lead frame or the portion to which a chip of a
Nam Kee Hwan
Noh Kil Seob
Smith Brad
Testa Hurwitz & Thibeault LLP
Zarabian Amir
LandOfFree
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