Tape device adapter

Boots – shoes – and leggings

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Details

G06F 1300, G06F 300, G06F 500

Patent

active

043420818

ABSTRACT:
A tape device adapter logic control system is disclosed for accommodating the transfer of control information and data of variable formats, densities, and logic level conventions between a medium performance device controller (MPDC) and mass storage devices. Information recorded in one processor code may be converted for use in a data processor having any other processor code, and may be packed or depacked to accommodate a change in density. Tristate logic is used to provide recursive data paths, thereby accommodating plural functions with minimal duplication of logic devices.
The MPDC loads control information into a device command register and an adapter command register of the tape device adapter to respectively provide control commands to device controllers and to the logic control system. The adapter command register controls the data flow through the tape adapter, and the operation of logic devices in the flow path to effect a 1.times.1, 4.times.3, 8.times.5, or 8.times.7 data packing or depacking, each with or without code conversion during either a data read or data write. With minor modifications in the logic control system of the tape device adapter, an 8.times.9 packing and depacking during read or write operations also may be accommodated. PISO (parallel-in-serial-out) shift registers are used in combination with FIFO (first-in-first-out) shift registers to effect a data packing or depacking. In addition, tri-state RAMs are configured to accommodate a change in conversion codes between data transfers during a data processing operation.

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patent: 4110830 (1978-08-01), Krygowski
patent: 4162520 (1979-07-01), Cook et al.

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